1a551c94aSIdo Barnea/*-
2a551c94aSIdo Barnea *   BSD LICENSE
3a551c94aSIdo Barnea *
4a551c94aSIdo Barnea *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
5a551c94aSIdo Barnea *   All rights reserved.
6a551c94aSIdo Barnea *
7a551c94aSIdo Barnea *   Redistribution and use in source and binary forms, with or without
8a551c94aSIdo Barnea *   modification, are permitted provided that the following conditions
9a551c94aSIdo Barnea *   are met:
10a551c94aSIdo Barnea *
11a551c94aSIdo Barnea *     * Redistributions of source code must retain the above copyright
12a551c94aSIdo Barnea *       notice, this list of conditions and the following disclaimer.
13a551c94aSIdo Barnea *     * Redistributions in binary form must reproduce the above copyright
14a551c94aSIdo Barnea *       notice, this list of conditions and the following disclaimer in
15a551c94aSIdo Barnea *       the documentation and/or other materials provided with the
16a551c94aSIdo Barnea *       distribution.
17a551c94aSIdo Barnea *     * Neither the name of Intel Corporation nor the names of its
18a551c94aSIdo Barnea *       contributors may be used to endorse or promote products derived
19a551c94aSIdo Barnea *       from this software without specific prior written permission.
20a551c94aSIdo Barnea *
32a551c94aSIdo Barnea */
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#include <stdio.h>
35a551c94aSIdo Barnea#include <stdint.h>
36a551c94aSIdo Barnea#include <stdarg.h>
37a551c94aSIdo Barnea#include <errno.h>
38a551c94aSIdo Barnea#include <sys/queue.h>
39a551c94aSIdo Barnea
40a551c94aSIdo Barnea#include <rte_interrupts.h>
41a551c94aSIdo Barnea#include <rte_log.h>
42a551c94aSIdo Barnea#include <rte_debug.h>
43a551c94aSIdo Barnea#include <rte_pci.h>
44a551c94aSIdo Barnea#include <rte_ether.h>
45a551c94aSIdo Barnea#include <rte_ethdev.h>
469ca4a157SIdo Barnea#include <rte_malloc.h>
47a551c94aSIdo Barnea
48a551c94aSIdo Barnea#include "ixgbe_logs.h"
49a551c94aSIdo Barnea#include "base/ixgbe_api.h"
50a551c94aSIdo Barnea#include "base/ixgbe_common.h"
51a551c94aSIdo Barnea#include "ixgbe_ethdev.h"
52a551c94aSIdo Barnea
53a551c94aSIdo Barnea/* To get PBALLOC (Packet Buffer Allocation) bits from FDIRCTRL value */
54a551c94aSIdo Barnea#define FDIRCTRL_PBALLOC_MASK           0x03
55a551c94aSIdo Barnea
56a551c94aSIdo Barnea/* For calculating memory required for FDIR filters */
57a551c94aSIdo Barnea#define PBALLOC_SIZE_SHIFT              15
58a551c94aSIdo Barnea
59a551c94aSIdo Barnea/* Number of bits used to mask bucket hash for different pballoc sizes */
60a551c94aSIdo Barnea#define PERFECT_BUCKET_64KB_HASH_MASK   0x07FF  /* 11 bits */
61a551c94aSIdo Barnea#define PERFECT_BUCKET_128KB_HASH_MASK  0x0FFF  /* 12 bits */
62a551c94aSIdo Barnea#define PERFECT_BUCKET_256KB_HASH_MASK  0x1FFF  /* 13 bits */
63a551c94aSIdo Barnea#define SIG_BUCKET_64KB_HASH_MASK       0x1FFF  /* 13 bits */
64a551c94aSIdo Barnea#define SIG_BUCKET_128KB_HASH_MASK      0x3FFF  /* 14 bits */
65a551c94aSIdo Barnea#define SIG_BUCKET_256KB_HASH_MASK      0x7FFF  /* 15 bits */
66a551c94aSIdo Barnea#define IXGBE_DEFAULT_FLEXBYTES_OFFSET  12 /* default flexbytes offset in bytes */
67a551c94aSIdo Barnea#define IXGBE_FDIR_MAX_FLEX_LEN         2 /* len in bytes of flexbytes */
68a551c94aSIdo Barnea#define IXGBE_MAX_FLX_SOURCE_OFF        62
69a551c94aSIdo Barnea#define IXGBE_FDIRCTRL_FLEX_MASK        (0x1F << IXGBE_FDIRCTRL_FLEX_SHIFT)
70a551c94aSIdo Barnea#define IXGBE_FDIRCMD_CMD_INTERVAL_US   10
71a551c94aSIdo Barnea
72a551c94aSIdo Barnea#define IXGBE_FDIR_FLOW_TYPES ( \
73a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
74a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
75a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
76a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
77a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
78a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
79a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
80a551c94aSIdo Barnea	(1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER))
81a551c94aSIdo Barnea
82a551c94aSIdo Barnea#define IPV6_ADDR_TO_MASK(ipaddr, ipv6m) do { \
83a551c94aSIdo Barnea	uint8_t ipv6_addr[16]; \
84a551c94aSIdo Barnea	uint8_t i; \
85a551c94aSIdo Barnea	rte_memcpy(ipv6_addr, (ipaddr), sizeof(ipv6_addr));\
86a551c94aSIdo Barnea	(ipv6m) = 0; \
87a551c94aSIdo Barnea	for (i = 0; i < sizeof(ipv6_addr); i++) { \
88a551c94aSIdo Barnea		if (ipv6_addr[i] == UINT8_MAX) \
89a551c94aSIdo Barnea			(ipv6m) |= 1 << i; \
90a551c94aSIdo Barnea		else if (ipv6_addr[i] != 0) { \
91a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, " invalid IPv6 address mask."); \
92a551c94aSIdo Barnea			return -EINVAL; \
93a551c94aSIdo Barnea		} \
94a551c94aSIdo Barnea	} \
95a551c94aSIdo Barnea} while (0)
96a551c94aSIdo Barnea
97a551c94aSIdo Barnea#define IPV6_MASK_TO_ADDR(ipv6m, ipaddr) do { \
98a551c94aSIdo Barnea	uint8_t ipv6_addr[16]; \
99a551c94aSIdo Barnea	uint8_t i; \
100a551c94aSIdo Barnea	for (i = 0; i < sizeof(ipv6_addr); i++) { \
101a551c94aSIdo Barnea		if ((ipv6m) & (1 << i)) \
102a551c94aSIdo Barnea			ipv6_addr[i] = UINT8_MAX; \
103a551c94aSIdo Barnea		else \
104a551c94aSIdo Barnea			ipv6_addr[i] = 0; \
105a551c94aSIdo Barnea	} \
106a551c94aSIdo Barnea	rte_memcpy((ipaddr), ipv6_addr, sizeof(ipv6_addr));\
107a551c94aSIdo Barnea} while (0)
108a551c94aSIdo Barnea
109a551c94aSIdo Barnea#define DEFAULT_VXLAN_PORT 4789
110a551c94aSIdo Barnea#define IXGBE_FDIRIP6M_INNER_MAC_SHIFT 4
111a551c94aSIdo Barnea
112a551c94aSIdo Barneastatic int fdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash);
113a551c94aSIdo Barneastatic int fdir_set_input_mask(struct rte_eth_dev *dev,
114a551c94aSIdo Barnea			       const struct rte_eth_fdir_masks *input_mask);
1159ca4a157SIdo Barneastatic int fdir_set_input_mask_82599(struct rte_eth_dev *dev);
1169ca4a157SIdo Barneastatic int fdir_set_input_mask_x550(struct rte_eth_dev *dev);
117a551c94aSIdo Barneastatic int ixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
118a551c94aSIdo Barnea		const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl);
119a551c94aSIdo Barneastatic int fdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl);
120a551c94aSIdo Barneastatic int ixgbe_fdir_filter_to_atr_input(
121a551c94aSIdo Barnea		const struct rte_eth_fdir_filter *fdir_filter,
122a551c94aSIdo Barnea		union ixgbe_atr_input *input,
123a551c94aSIdo Barnea		enum rte_fdir_mode mode);
124a551c94aSIdo Barneastatic uint32_t ixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
125a551c94aSIdo Barnea				 uint32_t key);
126a551c94aSIdo Barneastatic uint32_t atr_compute_sig_hash_82599(union ixgbe_atr_input *input,
127a551c94aSIdo Barnea		enum rte_fdir_pballoc_type pballoc);
128a551c94aSIdo Barneastatic uint32_t atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
129a551c94aSIdo Barnea		enum rte_fdir_pballoc_type pballoc);
130a551c94aSIdo Barneastatic int fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
131a551c94aSIdo Barnea			union ixgbe_atr_input *input, uint8_t queue,
132a551c94aSIdo Barnea			uint32_t fdircmd, uint32_t fdirhash,
133a551c94aSIdo Barnea			enum rte_fdir_mode mode);
134a551c94aSIdo Barneastatic int fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
135a551c94aSIdo Barnea		union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
136a551c94aSIdo Barnea		uint32_t fdirhash);
137a551c94aSIdo Barneastatic int ixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
138a551c94aSIdo Barnea			      const struct rte_eth_fdir_filter *fdir_filter,
139a551c94aSIdo Barnea			      bool del,
140a551c94aSIdo Barnea			      bool update);
141a551c94aSIdo Barneastatic int ixgbe_fdir_flush(struct rte_eth_dev *dev);
142a551c94aSIdo Barneastatic void ixgbe_fdir_info_get(struct rte_eth_dev *dev,
143a551c94aSIdo Barnea			struct rte_eth_fdir_info *fdir_info);
144a551c94aSIdo Barneastatic void ixgbe_fdir_stats_get(struct rte_eth_dev *dev,
145a551c94aSIdo Barnea			struct rte_eth_fdir_stats *fdir_stats);
146a551c94aSIdo Barnea
147a551c94aSIdo Barnea/**
148a551c94aSIdo Barnea * This function is based on ixgbe_fdir_enable_82599() in base/ixgbe_82599.c.
149a551c94aSIdo Barnea * It adds extra configuration of fdirctrl that is common for all filter types.
150a551c94aSIdo Barnea *
151a551c94aSIdo Barnea *  Initialize Flow Director control registers
152a551c94aSIdo Barnea *  @hw: pointer to hardware structure
153a551c94aSIdo Barnea *  @fdirctrl: value to write to flow director control register
154a551c94aSIdo Barnea **/
155a551c94aSIdo Barneastatic int
156a551c94aSIdo Barneafdir_enable_82599(struct ixgbe_hw *hw, uint32_t fdirctrl)
157a551c94aSIdo Barnea{
158a551c94aSIdo Barnea	int i;
159a551c94aSIdo Barnea
160a551c94aSIdo Barnea	PMD_INIT_FUNC_TRACE();
161a551c94aSIdo Barnea
162a551c94aSIdo Barnea	/* Prime the keys for hashing */
165a551c94aSIdo Barnea
166a551c94aSIdo Barnea	/*
167a551c94aSIdo Barnea	 * Continue setup of fdirctrl register bits:
168a551c94aSIdo Barnea	 *  Set the maximum length per hash bucket to 0xA filters
169a551c94aSIdo Barnea	 *  Send interrupt when 64 filters are left
170a551c94aSIdo Barnea	 */
171a551c94aSIdo Barnea	fdirctrl |= (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
172a551c94aSIdo Barnea		    (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
173a551c94aSIdo Barnea
174a551c94aSIdo Barnea	/*
175a551c94aSIdo Barnea	 * Poll init-done after we write the register.  Estimated times:
176a551c94aSIdo Barnea	 *      10G: PBALLOC = 11b, timing is 60us
177a551c94aSIdo Barnea	 *       1G: PBALLOC = 11b, timing is 600us
178a551c94aSIdo Barnea	 *     100M: PBALLOC = 11b, timing is 6ms
179a551c94aSIdo Barnea	 *
180a551c94aSIdo Barnea	 *     Multiple these timings by 4 if under full Rx load
181a551c94aSIdo Barnea	 *
182a551c94aSIdo Barnea	 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
183a551c94aSIdo Barnea	 * 1 msec per poll time.  If we're at line rate and drop to 100M, then
184a551c94aSIdo Barnea	 * this might not finish in our poll time, but we can live with that
185a551c94aSIdo Barnea	 * for now.
186a551c94aSIdo Barnea	 */
187a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
188a551c94aSIdo Barnea	IXGBE_WRITE_FLUSH(hw);
189a551c94aSIdo Barnea	for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
190a551c94aSIdo Barnea		if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
191a551c94aSIdo Barnea				   IXGBE_FDIRCTRL_INIT_DONE)
192a551c94aSIdo Barnea			break;
193a551c94aSIdo Barnea		msec_delay(1);
194a551c94aSIdo Barnea	}
195a551c94aSIdo Barnea
196a551c94aSIdo Barnea	if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
197a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "Flow Director poll time exceeded during enabling!");
198a551c94aSIdo Barnea		return -ETIMEDOUT;
199a551c94aSIdo Barnea	}
200a551c94aSIdo Barnea	return 0;
201a551c94aSIdo Barnea}
202a551c94aSIdo Barnea
203a551c94aSIdo Barnea/*
204a551c94aSIdo Barnea * Set appropriate bits in fdirctrl for: variable reporting levels, moving
205a551c94aSIdo Barnea * flexbytes matching field, and drop queue (only for perfect matching mode).
206a551c94aSIdo Barnea */
207a551c94aSIdo Barneastatic inline int
208a551c94aSIdo Barneaconfigure_fdir_flags(const struct rte_fdir_conf *conf, uint32_t *fdirctrl)
209a551c94aSIdo Barnea{
210a551c94aSIdo Barnea	*fdirctrl = 0;
211a551c94aSIdo Barnea
212a551c94aSIdo Barnea	switch (conf->pballoc) {
213a551c94aSIdo Barnea	case RTE_FDIR_PBALLOC_64K:
214a551c94aSIdo Barnea		/* 8k - 1 signature filters */
215a551c94aSIdo Barnea		*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_64K;
216a551c94aSIdo Barnea		break;
217a551c94aSIdo Barnea	case RTE_FDIR_PBALLOC_128K:
218a551c94aSIdo Barnea		/* 16k - 1 signature filters */
219a551c94aSIdo Barnea		*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_128K;
220a551c94aSIdo Barnea		break;
221a551c94aSIdo Barnea	case RTE_FDIR_PBALLOC_256K:
222a551c94aSIdo Barnea		/* 32k - 1 signature filters */
223a551c94aSIdo Barnea		*fdirctrl |= IXGBE_FDIRCTRL_PBALLOC_256K;
224a551c94aSIdo Barnea		break;
225a551c94aSIdo Barnea	default:
226a551c94aSIdo Barnea		/* bad value */
227a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "Invalid fdir_conf->pballoc value");
228a551c94aSIdo Barnea		return -EINVAL;
229a551c94aSIdo Barnea	};
230a551c94aSIdo Barnea
231a551c94aSIdo Barnea	/* status flags: write hash & swindex in the rx descriptor */
232a551c94aSIdo Barnea	switch (conf->status) {
233a551c94aSIdo Barnea	case RTE_FDIR_NO_REPORT_STATUS:
234a551c94aSIdo Barnea		/* do nothing, default mode */
235a551c94aSIdo Barnea		break;
236a551c94aSIdo Barnea	case RTE_FDIR_REPORT_STATUS:
237a551c94aSIdo Barnea		/* report status when the packet matches a fdir rule */
238a551c94aSIdo Barnea		*fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS;
239a551c94aSIdo Barnea		break;
240a551c94aSIdo Barnea	case RTE_FDIR_REPORT_STATUS_ALWAYS:
241a551c94aSIdo Barnea		/* always report status */
242a551c94aSIdo Barnea		*fdirctrl |= IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS;
243a551c94aSIdo Barnea		break;
244a551c94aSIdo Barnea	default:
245a551c94aSIdo Barnea		/* bad value */
246a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "Invalid fdir_conf->status value");
247a551c94aSIdo Barnea		return -EINVAL;
248a551c94aSIdo Barnea	};
249a551c94aSIdo Barnea
2503c0de05aSIdo Barnea#define TREX_PATCH
2513c0de05aSIdo Barnea#ifdef TREX_PATCH
2523c0de05aSIdo Barnea	*fdirctrl |= (conf->flexbytes_offset << IXGBE_FDIRCTRL_FLEX_SHIFT);
2533c0de05aSIdo Barnea#else
254a551c94aSIdo Barnea	*fdirctrl |= (IXGBE_DEFAULT_FLEXBYTES_OFFSET / sizeof(uint16_t)) <<
255a551c94aSIdo Barnea		     IXGBE_FDIRCTRL_FLEX_SHIFT;
2563c0de05aSIdo Barnea#endif
257a551c94aSIdo Barnea
258a551c94aSIdo Barnea	if (conf->mode >= RTE_FDIR_MODE_PERFECT &&
259a551c94aSIdo Barnea	    conf->mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
260a551c94aSIdo Barnea		*fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH;
261a551c94aSIdo Barnea		*fdirctrl |= (conf->drop_queue << IXGBE_FDIRCTRL_DROP_Q_SHIFT);
262a551c94aSIdo Barnea		if (conf->mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
263a551c94aSIdo Barnea			*fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_MACVLAN
264a551c94aSIdo Barnea					<< IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
265a551c94aSIdo Barnea		else if (conf->mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
266a551c94aSIdo Barnea			*fdirctrl |= (IXGBE_FDIRCTRL_FILTERMODE_CLOUD
267a551c94aSIdo Barnea					<< IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
268a551c94aSIdo Barnea	}
269a551c94aSIdo Barnea
270a551c94aSIdo Barnea	return 0;
271a551c94aSIdo Barnea}
272a551c94aSIdo Barnea
273a551c94aSIdo Barnea/**
274a551c94aSIdo Barnea * Reverse the bits in FDIR registers that store 2 x 16 bit masks.
275a551c94aSIdo Barnea *
276a551c94aSIdo Barnea *  @hi_dword: Bits 31:16 mask to be bit swapped.
277a551c94aSIdo Barnea *  @lo_dword: Bits 15:0  mask to be bit swapped.
278a551c94aSIdo Barnea *
279a551c94aSIdo Barnea *  Flow director uses several registers to store 2 x 16 bit masks with the
280a551c94aSIdo Barnea *  bits reversed such as FDIRTCPM, FDIRUDPM. The LS bit of the
281a551c94aSIdo Barnea *  mask affects the MS bit/byte of the target. This function reverses the
282a551c94aSIdo Barnea *  bits in these masks.
283a551c94aSIdo Barnea *  **/
284a551c94aSIdo Barneastatic inline uint32_t
285a551c94aSIdo Barneareverse_fdir_bitmasks(uint16_t hi_dword, uint16_t lo_dword)
286a551c94aSIdo Barnea{
287a551c94aSIdo Barnea	uint32_t mask = hi_dword << 16;
288a551c94aSIdo Barnea
289a551c94aSIdo Barnea	mask |= lo_dword;
290a551c94aSIdo Barnea	mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
291a551c94aSIdo Barnea	mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
292a551c94aSIdo Barnea	mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
293a551c94aSIdo Barnea	return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
294a551c94aSIdo Barnea}
295a551c94aSIdo Barnea
296a551c94aSIdo Barnea/*
297a551c94aSIdo Barnea * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
298a551c94aSIdo Barnea * but makes use of the rte_fdir_masks structure to see which bits to set.
299a551c94aSIdo Barnea */
300a551c94aSIdo Barneastatic int
3019ca4a157SIdo Barneafdir_set_input_mask_82599(struct rte_eth_dev *dev)
302a551c94aSIdo Barnea{
303a551c94aSIdo Barnea	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
304a551c94aSIdo Barnea	struct ixgbe_hw_fdir_info *info =
305a551c94aSIdo Barnea			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
306a551c94aSIdo Barnea	/*
307a551c94aSIdo Barnea	 * mask VM pool and DIPv6 since there are currently not supported
308a551c94aSIdo Barnea	 * mask FLEX byte, it will be set in flex_conf
309a551c94aSIdo Barnea	 */
310a551c94aSIdo Barnea	uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 | IXGBE_FDIRM_FLEX;
311a551c94aSIdo Barnea	uint32_t fdirtcpm;  /* TCP source and destination port masks. */
312a551c94aSIdo Barnea	uint32_t fdiripv6m; /* IPv6 source and destination masks. */
313a551c94aSIdo Barnea	volatile uint32_t *reg;
314a551c94aSIdo Barnea
315a551c94aSIdo Barnea	PMD_INIT_FUNC_TRACE();
316a551c94aSIdo Barnea
317a551c94aSIdo Barnea	/*
318a551c94aSIdo Barnea	 * Program the relevant mask registers.  If src/dst_port or src/dst_addr
319a551c94aSIdo Barnea	 * are zero, then assume a full mask for that field. Also assume that
320a551c94aSIdo Barnea	 * a VLAN of 0 is unspecified, so mask that out as well.  L4type
321a551c94aSIdo Barnea	 * cannot be masked out in this implementation.
322a551c94aSIdo Barnea	 */
3239ca4a157SIdo Barnea	if (info->mask.dst_port_mask == 0 && info->mask.src_port_mask == 0)
324a551c94aSIdo Barnea		/* use the L4 protocol mask for raw IPv4/IPv6 traffic */
325a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_L4P;
326a551c94aSIdo Barnea
3279ca4a157SIdo Barnea	if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
328a551c94aSIdo Barnea		/* mask VLAN Priority */
329a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_VLANP;
3309ca4a157SIdo Barnea	else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
331a551c94aSIdo Barnea		/* mask VLAN ID */
332a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_VLANID;
3339ca4a157SIdo Barnea	else if (info->mask.vlan_tci_mask == 0)
334a551c94aSIdo Barnea		/* mask VLAN ID and Priority */
335a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
3369ca4a157SIdo Barnea	else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
337a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
338a551c94aSIdo Barnea		return -EINVAL;
339a551c94aSIdo Barnea	}
340a551c94aSIdo Barnea
341a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
342a551c94aSIdo Barnea
343a551c94aSIdo Barnea	/* store the TCP/UDP port masks, bit reversed from port layout */
344a551c94aSIdo Barnea	fdirtcpm = reverse_fdir_bitmasks(
3459ca4a157SIdo Barnea			rte_be_to_cpu_16(info->mask.dst_port_mask),
3469ca4a157SIdo Barnea			rte_be_to_cpu_16(info->mask.src_port_mask));
347a551c94aSIdo Barnea
348a551c94aSIdo Barnea	/* write all the same so that UDP, TCP and SCTP use the same mask
349a551c94aSIdo Barnea	 * (little-endian)
350a551c94aSIdo Barnea	 */
351a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
352a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
353a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
354a551c94aSIdo Barnea
355a551c94aSIdo Barnea	/* Store source and destination IPv4 masks (big-endian),
356a551c94aSIdo Barnea	 * can not use IXGBE_WRITE_REG.
357a551c94aSIdo Barnea	 */
358a551c94aSIdo Barnea	reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRSIP4M);
3599ca4a157SIdo Barnea	*reg = ~(info->mask.src_ipv4_mask);
360a551c94aSIdo Barnea	reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRDIP4M);
3619ca4a157SIdo Barnea	*reg = ~(info->mask.dst_ipv4_mask);
362a551c94aSIdo Barnea
363a551c94aSIdo Barnea	if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_SIGNATURE) {
364a551c94aSIdo Barnea		/*
365a551c94aSIdo Barnea		 * Store source and destination IPv6 masks (bit reversed)
366a551c94aSIdo Barnea		 */
3679ca4a157SIdo Barnea		fdiripv6m = (info->mask.dst_ipv6_mask << 16) |
3689ca4a157SIdo Barnea			    info->mask.src_ipv6_mask;
369a551c94aSIdo Barnea
370a551c94aSIdo Barnea		IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, ~fdiripv6m);
371a551c94aSIdo Barnea	}
372a551c94aSIdo Barnea
373a551c94aSIdo Barnea	return IXGBE_SUCCESS;
374a551c94aSIdo Barnea}
375a551c94aSIdo Barnea
376a551c94aSIdo Barnea/*
377a551c94aSIdo Barnea * This references ixgbe_fdir_set_input_mask_82599() in base/ixgbe_82599.c,
378a551c94aSIdo Barnea * but makes use of the rte_fdir_masks structure to see which bits to set.
379a551c94aSIdo Barnea */
380a551c94aSIdo Barneastatic int
3819ca4a157SIdo Barneafdir_set_input_mask_x550(struct rte_eth_dev *dev)
382a551c94aSIdo Barnea{
383a551c94aSIdo Barnea	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
384a551c94aSIdo Barnea	struct ixgbe_hw_fdir_info *info =
385a551c94aSIdo Barnea			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
386a551c94aSIdo Barnea	/* mask VM pool and DIPv6 since there are currently not supported
387a551c94aSIdo Barnea	 * mask FLEX byte, it will be set in flex_conf
388a551c94aSIdo Barnea	 */
389a551c94aSIdo Barnea	uint32_t fdirm = IXGBE_FDIRM_POOL | IXGBE_FDIRM_DIPv6 |
390a551c94aSIdo Barnea			 IXGBE_FDIRM_FLEX;
391a551c94aSIdo Barnea	uint32_t fdiripv6m;
392a551c94aSIdo Barnea	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
393a551c94aSIdo Barnea	uint16_t mac_mask;
394a551c94aSIdo Barnea
395a551c94aSIdo Barnea	PMD_INIT_FUNC_TRACE();
396a551c94aSIdo Barnea
397a551c94aSIdo Barnea	/* set the default UDP port for VxLAN */
398a551c94aSIdo Barnea	if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL)
400a551c94aSIdo Barnea
401a551c94aSIdo Barnea	/* some bits must be set for mac vlan or tunnel mode */
402a551c94aSIdo Barnea	fdirm |= IXGBE_FDIRM_L4P | IXGBE_FDIRM_L3P;
403a551c94aSIdo Barnea
4049ca4a157SIdo Barnea	if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0x0FFF))
405a551c94aSIdo Barnea		/* mask VLAN Priority */
406a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_VLANP;
4079ca4a157SIdo Barnea	else if (info->mask.vlan_tci_mask == rte_cpu_to_be_16(0xE000))
408a551c94aSIdo Barnea		/* mask VLAN ID */
409a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_VLANID;
4109ca4a157SIdo Barnea	else if (info->mask.vlan_tci_mask == 0)
411a551c94aSIdo Barnea		/* mask VLAN ID and Priority */
412a551c94aSIdo Barnea		fdirm |= IXGBE_FDIRM_VLANID | IXGBE_FDIRM_VLANP;
4139ca4a157SIdo Barnea	else if (info->mask.vlan_tci_mask != rte_cpu_to_be_16(0xEFFF)) {
414a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "invalid vlan_tci_mask");
415a551c94aSIdo Barnea		return -EINVAL;
416a551c94aSIdo Barnea	}
417a551c94aSIdo Barnea
418a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
419a551c94aSIdo Barnea
420a551c94aSIdo Barnea	fdiripv6m = ((u32)0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
421a551c94aSIdo Barnea	fdiripv6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
422a551c94aSIdo Barnea	if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN)
423a551c94aSIdo Barnea		fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE |
424a551c94aSIdo Barnea				IXGBE_FDIRIP6M_TNI_VNI;
425a551c94aSIdo Barnea
426a551c94aSIdo Barnea	if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
4279ca4a157SIdo Barnea		mac_mask = info->mask.mac_addr_byte_mask;
4289ca4a157SIdo Barnea		fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)
4299ca4a157SIdo Barnea				& IXGBE_FDIRIP6M_INNER_MAC;
4309ca4a157SIdo Barnea
4319ca4a157SIdo Barnea		switch (info->mask.tunnel_type_mask) {
432a551c94aSIdo Barnea		case 0:
433a551c94aSIdo Barnea			/* Mask turnnel type */
434a551c94aSIdo Barnea			fdiripv6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
435a551c94aSIdo Barnea			break;
436a551c94aSIdo Barnea		case 1:
437a551c94aSIdo Barnea			break;
438a551c94aSIdo Barnea		default:
439a551c94aSIdo Barnea			PMD_INIT_LOG(ERR, "invalid tunnel_type_mask");
440a551c94aSIdo Barnea			return -EINVAL;
441a551c94aSIdo Barnea		}
442a551c94aSIdo Barnea
4439ca4a157SIdo Barnea		switch (rte_be_to_cpu_32(info->mask.tunnel_id_mask)) {
444a551c94aSIdo Barnea		case 0x0:
445a551c94aSIdo Barnea			/* Mask vxlan id */
446a551c94aSIdo Barnea			fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI;
447a551c94aSIdo Barnea			break;
448a551c94aSIdo Barnea		case 0x00FFFFFF:
449a551c94aSIdo Barnea			fdiripv6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
450a551c94aSIdo Barnea			break;
451a551c94aSIdo Barnea		case 0xFFFFFFFF:
452a551c94aSIdo Barnea			break;
453a551c94aSIdo Barnea		default:
454a551c94aSIdo Barnea			PMD_INIT_LOG(ERR, "invalid tunnel_id_mask");
455a551c94aSIdo Barnea			return -EINVAL;
456a551c94aSIdo Barnea		}
457a551c94aSIdo Barnea	}
458a551c94aSIdo Barnea
459a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRIP6M, fdiripv6m);
465a551c94aSIdo Barnea
466a551c94aSIdo Barnea	return IXGBE_SUCCESS;
467a551c94aSIdo Barnea}
468a551c94aSIdo Barnea
469a551c94aSIdo Barneastatic int
4709ca4a157SIdo Barneaixgbe_fdir_store_input_mask_82599(struct rte_eth_dev *dev,
4719ca4a157SIdo Barnea				  const struct rte_eth_fdir_masks *input_mask)
4729ca4a157SIdo Barnea{
4739ca4a157SIdo Barnea	struct ixgbe_hw_fdir_info *info =
4749ca4a157SIdo Barnea		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
4759ca4a157SIdo Barnea	uint16_t dst_ipv6m = 0;
4769ca4a157SIdo Barnea	uint16_t src_ipv6m = 0;
4779ca4a157SIdo Barnea
4789ca4a157SIdo Barnea	memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
4799ca4a157SIdo Barnea	info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
4809ca4a157SIdo Barnea	info->mask.src_port_mask = input_mask->src_port_mask;
4819ca4a157SIdo Barnea	info->mask.dst_port_mask = input_mask->dst_port_mask;
4829ca4a157SIdo Barnea	info->mask.src_ipv4_mask = input_mask->ipv4_mask.src_ip;
4839ca4a157SIdo Barnea	info->mask.dst_ipv4_mask = input_mask->ipv4_mask.dst_ip;
4849ca4a157SIdo Barnea	IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.src_ip, src_ipv6m);
4859ca4a157SIdo Barnea	IPV6_ADDR_TO_MASK(input_mask->ipv6_mask.dst_ip, dst_ipv6m);
4869ca4a157SIdo Barnea	info->mask.src_ipv6_mask = src_ipv6m;
4879ca4a157SIdo Barnea	info->mask.dst_ipv6_mask = dst_ipv6m;
4889ca4a157SIdo Barnea
4899ca4a157SIdo Barnea	return IXGBE_SUCCESS;
4909ca4a157SIdo Barnea}
4919ca4a157SIdo Barnea
4929ca4a157SIdo Barneastatic int
4939ca4a157SIdo Barneaixgbe_fdir_store_input_mask_x550(struct rte_eth_dev *dev,
4949ca4a157SIdo Barnea				 const struct rte_eth_fdir_masks *input_mask)
4959ca4a157SIdo Barnea{
4969ca4a157SIdo Barnea	struct ixgbe_hw_fdir_info *info =
4979ca4a157SIdo Barnea		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
4989ca4a157SIdo Barnea
4999ca4a157SIdo Barnea	memset(&info->mask, 0, sizeof(struct ixgbe_hw_fdir_mask));
5009ca4a157SIdo Barnea	info->mask.vlan_tci_mask = input_mask->vlan_tci_mask;
5019ca4a157SIdo Barnea	info->mask.mac_addr_byte_mask = input_mask->mac_addr_byte_mask;
5029ca4a157SIdo Barnea	info->mask.tunnel_type_mask = input_mask->tunnel_type_mask;
5039ca4a157SIdo Barnea	info->mask.tunnel_id_mask = input_mask->tunnel_id_mask;
5049ca4a157SIdo Barnea
5059ca4a157SIdo Barnea	return IXGBE_SUCCESS;
5069ca4a157SIdo Barnea}
5079ca4a157SIdo Barnea
5089ca4a157SIdo Barneastatic int
5099ca4a157SIdo Barneaixgbe_fdir_store_input_mask(struct rte_eth_dev *dev,
5109ca4a157SIdo Barnea			    const struct rte_eth_fdir_masks *input_mask)
5119ca4a157SIdo Barnea{
5129ca4a157SIdo Barnea	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
5139ca4a157SIdo Barnea
5149ca4a157SIdo Barnea	if (mode >= RTE_FDIR_MODE_SIGNATURE &&
5159ca4a157SIdo Barnea	    mode <= RTE_FDIR_MODE_PERFECT)
5169ca4a157SIdo Barnea		return ixgbe_fdir_store_input_mask_82599(dev, input_mask);
5179ca4a157SIdo Barnea	else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
5189ca4a157SIdo Barnea		 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
5199ca4a157SIdo Barnea		return ixgbe_fdir_store_input_mask_x550(dev, input_mask);
5209ca4a157SIdo Barnea
5219ca4a157SIdo Barnea	PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
5229ca4a157SIdo Barnea	return -ENOTSUP;
5239ca4a157SIdo Barnea}
5249ca4a157SIdo Barnea
5259ca4a157SIdo Barneaint
5269ca4a157SIdo Barneaixgbe_fdir_set_input_mask(struct rte_eth_dev *dev)
527a551c94aSIdo Barnea{
528a551c94aSIdo Barnea	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
529a551c94aSIdo Barnea
530a551c94aSIdo Barnea	if (mode >= RTE_FDIR_MODE_SIGNATURE &&
531a551c94aSIdo Barnea	    mode <= RTE_FDIR_MODE_PERFECT)
5329ca4a157SIdo Barnea		return fdir_set_input_mask_82599(dev);
533a551c94aSIdo Barnea	else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
534a551c94aSIdo Barnea		 mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
5359ca4a157SIdo Barnea		return fdir_set_input_mask_x550(dev);
536a551c94aSIdo Barnea
537a551c94aSIdo Barnea	PMD_DRV_LOG(ERR, "Not supported fdir mode - %d!", mode);
538a551c94aSIdo Barnea	return -ENOTSUP;
539a551c94aSIdo Barnea}
540a551c94aSIdo Barnea
5419ca4a157SIdo Barneastatic int
5429ca4a157SIdo Barneafdir_set_input_mask(struct rte_eth_dev *dev,
5439ca4a157SIdo Barnea		    const struct rte_eth_fdir_masks *input_mask)
5449ca4a157SIdo Barnea{
5459ca4a157SIdo Barnea	int ret;
5469ca4a157SIdo Barnea
5479ca4a157SIdo Barnea	ret = ixgbe_fdir_store_input_mask(dev, input_mask);
5489ca4a157SIdo Barnea	if (ret)
5499ca4a157SIdo Barnea		return ret;
5509ca4a157SIdo Barnea
5519ca4a157SIdo Barnea	return ixgbe_fdir_set_input_mask(dev);
5529ca4a157SIdo Barnea}
5539ca4a157SIdo Barnea
554a551c94aSIdo Barnea/*
555a551c94aSIdo Barnea * ixgbe_check_fdir_flex_conf -check if the flex payload and mask configuration
556a551c94aSIdo Barnea * arguments are valid
557a551c94aSIdo Barnea */
558a551c94aSIdo Barneastatic int
559a551c94aSIdo Barneaixgbe_set_fdir_flex_conf(struct rte_eth_dev *dev,
560a551c94aSIdo Barnea		const struct rte_eth_fdir_flex_conf *conf, uint32_t *fdirctrl)
561a551c94aSIdo Barnea{
562a551c94aSIdo Barnea	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
563a551c94aSIdo Barnea	struct ixgbe_hw_fdir_info *info =
564a551c94aSIdo Barnea			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
565a551c94aSIdo Barnea	const struct rte_eth_flex_payload_cfg *flex_cfg;
566a551c94aSIdo Barnea	const struct rte_eth_fdir_flex_mask *flex_mask;
567a551c94aSIdo Barnea	uint32_t fdirm;
568a551c94aSIdo Barnea	uint16_t flexbytes = 0;
569a551c94aSIdo Barnea	uint16_t i;
570a551c94aSIdo Barnea
571a551c94aSIdo Barnea	fdirm = IXGBE_READ_REG(hw, IXGBE_FDIRM);
5723c0de05aSIdo Barnea#ifndef TREX_PATCH
573a551c94aSIdo Barnea	if (conf == NULL) {
574a551c94aSIdo Barnea		PMD_DRV_LOG(ERR, "NULL pointer.");
575a551c94aSIdo Barnea		return -EINVAL;
576a551c94aSIdo Barnea	}
577a551c94aSIdo Barnea
578a551c94aSIdo Barnea	for (i = 0; i < conf->nb_payloads; i++) {
579a551c94aSIdo Barnea		flex_cfg = &conf->flex_set[i];
580a551c94aSIdo Barnea		if (flex_cfg->type != RTE_ETH_RAW_PAYLOAD) {
581a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, "unsupported payload type.");
582a551c94aSIdo Barnea			return -EINVAL;
583a551c94aSIdo Barnea		}
584a551c94aSIdo Barnea		if (((flex_cfg->src_offset[0] & 0x1) == 0) &&
585a551c94aSIdo Barnea		    (flex_cfg->src_offset[1] == flex_cfg->src_offset[0] + 1) &&
586a551c94aSIdo Barnea		    (flex_cfg->src_offset[0] <= IXGBE_MAX_FLX_SOURCE_OFF)) {
587a551c94aSIdo Barnea			*fdirctrl &= ~IXGBE_FDIRCTRL_FLEX_MASK;
588a551c94aSIdo Barnea			*fdirctrl |=
589a551c94aSIdo Barnea				(flex_cfg->src_offset[0] / sizeof(uint16_t)) <<
590a551c94aSIdo Barnea					IXGBE_FDIRCTRL_FLEX_SHIFT;
591a551c94aSIdo Barnea		} else {
592a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, "invalid flexbytes arguments.");
593a551c94aSIdo Barnea			return -EINVAL;
594a551c94aSIdo Barnea		}
595a551c94aSIdo Barnea	}
596a551c94aSIdo Barnea
597a551c94aSIdo Barnea	for (i = 0; i < conf->nb_flexmasks; i++) {
598a551c94aSIdo Barnea		flex_mask = &conf->flex_mask[i];
599a551c94aSIdo Barnea		if (flex_mask->flow_type != RTE_ETH_FLOW_UNKNOWN) {
600a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, "flexmask should be set globally.");
601a551c94aSIdo Barnea			return -EINVAL;
602a551c94aSIdo Barnea		}
603a551c94aSIdo Barnea		flexbytes = (uint16_t)(((flex_mask->mask[0] << 8) & 0xFF00) |
604a551c94aSIdo Barnea					((flex_mask->mask[1]) & 0xFF));
605a551c94aSIdo Barnea		if (flexbytes == UINT16_MAX)
606a551c94aSIdo Barnea			fdirm &= ~IXGBE_FDIRM_FLEX;
607a551c94aSIdo Barnea		else if (flexbytes != 0) {
608a551c94aSIdo Barnea			/* IXGBE_FDIRM_FLEX is set by default when set mask */
609a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, " invalid flexbytes mask arguments.");
610a551c94aSIdo Barnea			return -EINVAL;
611a551c94aSIdo Barnea		}
612a551c94aSIdo Barnea	}
6133c0de05aSIdo Barnea#else
6143c0de05aSIdo Barnea        fdirm &= ~IXGBE_FDIRM_FLEX;
6153c0de05aSIdo Barnea        flexbytes = 1;
6163c0de05aSIdo Barnea        // fdirctrl gets flex_bytes_offset in configure_fdir_flags
6173c0de05aSIdo Barnea#endif
618a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
619a551c94aSIdo Barnea	info->mask.flex_bytes_mask = flexbytes ? UINT16_MAX : 0;
620a551c94aSIdo Barnea	info->flex_bytes_offset = (uint8_t)((*fdirctrl &
621a551c94aSIdo Barnea					    IXGBE_FDIRCTRL_FLEX_MASK) >>
622a551c94aSIdo Barnea					    IXGBE_FDIRCTRL_FLEX_SHIFT);
623a551c94aSIdo Barnea	return 0;
624a551c94aSIdo Barnea}
625a551c94aSIdo Barnea
626a551c94aSIdo Barneaint
627a551c94aSIdo Barneaixgbe_fdir_configure(struct rte_eth_dev *dev)
628a551c94aSIdo Barnea{
629a551c94aSIdo Barnea	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
630a551c94aSIdo Barnea	int err;
631a551c94aSIdo Barnea	uint32_t fdirctrl, pbsize;
632a551c94aSIdo Barnea	int i;
633a551c94aSIdo Barnea	enum rte_fdir_mode mode = dev->data->dev_conf.fdir_conf.mode;
634a551c94aSIdo Barnea
635a551c94aSIdo Barnea	PMD_INIT_FUNC_TRACE();
636a551c94aSIdo Barnea
637a551c94aSIdo Barnea	if (hw->mac.type != ixgbe_mac_82599EB &&
638a551c94aSIdo Barnea		hw->mac.type != ixgbe_mac_X540 &&
639a551c94aSIdo Barnea		hw->mac.type != ixgbe_mac_X550 &&
640a551c94aSIdo Barnea		hw->mac.type != ixgbe_mac_X550EM_x &&
641a551c94aSIdo Barnea		hw->mac.type != ixgbe_mac_X550EM_a)
642a551c94aSIdo Barnea		return -ENOSYS;
643a551c94aSIdo Barnea
644a551c94aSIdo Barnea	/* x550 supports mac-vlan and tunnel mode but other NICs not */
645a551c94aSIdo Barnea	if (hw->mac.type != ixgbe_mac_X550 &&
646a551c94aSIdo Barnea	    hw->mac.type != ixgbe_mac_X550EM_x &&
647a551c94aSIdo Barnea	    hw->mac.type != ixgbe_mac_X550EM_a &&
648a551c94aSIdo Barnea	    mode != RTE_FDIR_MODE_SIGNATURE &&
6493c0de05aSIdo Barnea#ifdef TREX_PATCH
6503c0de05aSIdo Barnea	    mode != RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
6513c0de05aSIdo Barnea#endif
652a551c94aSIdo Barnea	    mode != RTE_FDIR_MODE_PERFECT)
653a551c94aSIdo Barnea		return -ENOSYS;
654a551c94aSIdo Barnea
655a551c94aSIdo Barnea	err = configure_fdir_flags(&dev->data->dev_conf.fdir_conf, &fdirctrl);
656a551c94aSIdo Barnea	if (err)
657a551c94aSIdo Barnea		return err;
658a551c94aSIdo Barnea
659a551c94aSIdo Barnea	/*
660a551c94aSIdo Barnea	 * Before enabling Flow Director, the Rx Packet Buffer size
661a551c94aSIdo Barnea	 * must be reduced.  The new value is the current size minus
662a551c94aSIdo Barnea	 * flow director memory usage size.
663a551c94aSIdo Barnea	 */
664a551c94aSIdo Barnea	pbsize = (1 << (PBALLOC_SIZE_SHIFT + (fdirctrl & FDIRCTRL_PBALLOC_MASK)));
665a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0),
666a551c94aSIdo Barnea	    (IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(0)) - pbsize));
667a551c94aSIdo Barnea
668a551c94aSIdo Barnea	/*
669a551c94aSIdo Barnea	 * The defaults in the HW for RX PB 1-7 are not zero and so should be
670a551c94aSIdo Barnea	 * intialized to zero for non DCB mode otherwise actual total RX PB
671a551c94aSIdo Barnea	 * would be bigger than programmed and filter space would run into
672a551c94aSIdo Barnea	 * the PB 0 region.
673a551c94aSIdo Barnea	 */
674a551c94aSIdo Barnea	for (i = 1; i < 8; i++)
675a551c94aSIdo Barnea		IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
676a551c94aSIdo Barnea
677a551c94aSIdo Barnea	err = fdir_set_input_mask(dev, &dev->data->dev_conf.fdir_conf.mask);
678a551c94aSIdo Barnea	if (err < 0) {
679a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, " Error on setting FD mask");
680a551c94aSIdo Barnea		return err;
681a551c94aSIdo Barnea	}
682a551c94aSIdo Barnea	err = ixgbe_set_fdir_flex_conf(dev,
683a551c94aSIdo Barnea		&dev->data->dev_conf.fdir_conf.flex_conf, &fdirctrl);
684a551c94aSIdo Barnea	if (err < 0) {
685a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, " Error on setting FD flexible arguments.");
686a551c94aSIdo Barnea		return err;
687a551c94aSIdo Barnea	}
688a551c94aSIdo Barnea
689a551c94aSIdo Barnea	err = fdir_enable_82599(hw, fdirctrl);
690a551c94aSIdo Barnea	if (err < 0) {
691a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, " Error on enabling FD.");
692a551c94aSIdo Barnea		return err;
693a551c94aSIdo Barnea	}
694a551c94aSIdo Barnea	return 0;
695a551c94aSIdo Barnea}
696a551c94aSIdo Barnea
697a551c94aSIdo Barnea/*
698a551c94aSIdo Barnea * Convert DPDK rte_eth_fdir_filter struct to ixgbe_atr_input union that is used
699a551c94aSIdo Barnea * by the IXGBE driver code.
700a551c94aSIdo Barnea */
701a551c94aSIdo Barneastatic int
702a551c94aSIdo Barneaixgbe_fdir_filter_to_atr_input(const struct rte_eth_fdir_filter *fdir_filter,
703a551c94aSIdo Barnea		union ixgbe_atr_input *input, enum rte_fdir_mode mode)
704a551c94aSIdo Barnea{
705a551c94aSIdo Barnea	input->formatted.vlan_id = fdir_filter->input.flow_ext.vlan_tci;
706a551c94aSIdo Barnea	input->formatted.flex_bytes = (uint16_t)(
707a551c94aSIdo Barnea		(fdir_filter->input.flow_ext.flexbytes[1] << 8 & 0xFF00) |
708a551c94aSIdo Barnea		(fdir_filter->input.flow_ext.flexbytes[0] & 0xFF));
709a551c94aSIdo Barnea
710a551c94aSIdo Barnea	switch (fdir_filter->input.flow_type) {
711a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
712a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV4;
713a551c94aSIdo Barnea		break;
714a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
715a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
716a551c94aSIdo Barnea		break;
717a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
718a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV4;
719a551c94aSIdo Barnea		break;
720a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
721a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV4;
722a551c94aSIdo Barnea		break;
723a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
724a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_UDPV6;
725a551c94aSIdo Barnea		break;
726a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
727a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
728a551c94aSIdo Barnea		break;
729a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
730a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_SCTPV6;
731a551c94aSIdo Barnea		break;
732a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
733a551c94aSIdo Barnea		input->formatted.flow_type = IXGBE_ATR_FLOW_TYPE_IPV6;
734a551c94aSIdo Barnea		break;
735a551c94aSIdo Barnea	default:
736a551c94aSIdo Barnea		break;
737a551c94aSIdo Barnea	}
738a551c94aSIdo Barnea
739a551c94aSIdo Barnea	switch (fdir_filter->input.flow_type) {
740a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
741a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
742a551c94aSIdo Barnea		input->formatted.src_port =
743a551c94aSIdo Barnea			fdir_filter->input.flow.udp4_flow.src_port;
744a551c94aSIdo Barnea		input->formatted.dst_port =
745a551c94aSIdo Barnea			fdir_filter->input.flow.udp4_flow.dst_port;
746a551c94aSIdo Barnea	/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
747a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
748a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
749a551c94aSIdo Barnea		input->formatted.src_ip[0] =
750a551c94aSIdo Barnea			fdir_filter->input.flow.ip4_flow.src_ip;
751a551c94aSIdo Barnea		input->formatted.dst_ip[0] =
752a551c94aSIdo Barnea			fdir_filter->input.flow.ip4_flow.dst_ip;
753a551c94aSIdo Barnea		break;
754a551c94aSIdo Barnea
755a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
756a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
757a551c94aSIdo Barnea		input->formatted.src_port =
758a551c94aSIdo Barnea			fdir_filter->input.flow.udp6_flow.src_port;
759a551c94aSIdo Barnea		input->formatted.dst_port =
760a551c94aSIdo Barnea			fdir_filter->input.flow.udp6_flow.dst_port;
761a551c94aSIdo Barnea	/*for SCTP flow type, port and verify_tag are meaningless in ixgbe.*/
762a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
763a551c94aSIdo Barnea	case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
764a551c94aSIdo Barnea		rte_memcpy(input->formatted.src_ip,
765a551c94aSIdo Barnea			   fdir_filter->input.flow.ipv6_flow.src_ip,
766a551c94aSIdo Barnea			   sizeof(input->formatted.src_ip));
767a551c94aSIdo Barnea		rte_memcpy(input->formatted.dst_ip,
768a551c94aSIdo Barnea			   fdir_filter->input.flow.ipv6_flow.dst_ip,
769a551c94aSIdo Barnea			   sizeof(input->formatted.dst_ip));
770a551c94aSIdo Barnea		break;
771a551c94aSIdo Barnea	default:
772a551c94aSIdo Barnea		break;
773a551c94aSIdo Barnea	}
774a551c94aSIdo Barnea
775a551c94aSIdo Barnea	if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
776a551c94aSIdo Barnea		rte_memcpy(
777a551c94aSIdo Barnea			input->formatted.inner_mac,
778a551c94aSIdo Barnea			fdir_filter->input.flow.mac_vlan_flow.mac_addr.addr_bytes,
779a551c94aSIdo Barnea			sizeof(input->formatted.inner_mac));
780a551c94aSIdo Barnea	} else if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
781a551c94aSIdo Barnea		rte_memcpy(
782a551c94aSIdo Barnea			input->formatted.inner_mac,
783a551c94aSIdo Barnea			fdir_filter->input.flow.tunnel_flow.mac_addr.addr_bytes,
784a551c94aSIdo Barnea			sizeof(input->formatted.inner_mac));
785a551c94aSIdo Barnea		input->formatted.tunnel_type =
786a551c94aSIdo Barnea			fdir_filter->input.flow.tunnel_flow.tunnel_type;
787a551c94aSIdo Barnea		input->formatted.tni_vni =
788a551c94aSIdo Barnea			fdir_filter->input.flow.tunnel_flow.tunnel_id;
789a551c94aSIdo Barnea	}
790a551c94aSIdo Barnea
791a551c94aSIdo Barnea	return 0;
792a551c94aSIdo Barnea}
793a551c94aSIdo Barnea
794a551c94aSIdo Barnea/*
795a551c94aSIdo Barnea * The below function is taken from the FreeBSD IXGBE drivers release
796a551c94aSIdo Barnea * 2.3.8. The only change is not to mask hash_result with IXGBE_ATR_HASH_MASK
797a551c94aSIdo Barnea * before returning, as the signature hash can use 16bits.
798a551c94aSIdo Barnea *
799a551c94aSIdo Barnea * The newer driver has optimised functions for calculating bucket and
800a551c94aSIdo Barnea * signature hashes. However they don't support IPv6 type packets for signature
801a551c94aSIdo Barnea * filters so are not used here.
802a551c94aSIdo Barnea *
803a551c94aSIdo Barnea * Note that the bkt_hash field in the ixgbe_atr_input structure is also never
804a551c94aSIdo Barnea * set.
805a551c94aSIdo Barnea *
806a551c94aSIdo Barnea * Compute the hashes for SW ATR
807a551c94aSIdo Barnea *  @stream: input bitstream to compute the hash on
808a551c94aSIdo Barnea *  @key: 32-bit hash key
809a551c94aSIdo Barnea **/
810a551c94aSIdo Barneastatic uint32_t
811a551c94aSIdo Barneaixgbe_atr_compute_hash_82599(union ixgbe_atr_input *atr_input,
812a551c94aSIdo Barnea				 uint32_t key)
813a551c94aSIdo Barnea{
814a551c94aSIdo Barnea	/*
815a551c94aSIdo Barnea	 * The algorithm is as follows:
816a551c94aSIdo Barnea	 *    Hash[15:0] = Sum { S[n] x K[n+16] }, n = 0...350
817a551c94aSIdo Barnea	 *    where Sum {A[n]}, n = 0...n is bitwise XOR of A[0], A[1]...A[n]
818a551c94aSIdo Barnea	 *    and A[n] x B[n] is bitwise AND between same length strings
819a551c94aSIdo Barnea	 *
820a551c94aSIdo Barnea	 *    K[n] is 16 bits, defined as:
821a551c94aSIdo Barnea	 *       for n modulo 32 >= 15, K[n] = K[n % 32 : (n % 32) - 15]
822a551c94aSIdo Barnea	 *       for n modulo 32 < 15, K[n] =
823a551c94aSIdo Barnea	 *             K[(n % 32:0) | (31:31 - (14 - (n % 32)))]
824a551c94aSIdo Barnea	 *
825a551c94aSIdo Barnea	 *    S[n] is 16 bits, defined as:
826a551c94aSIdo Barnea	 *       for n >= 15, S[n] = S[n:n - 15]
827a551c94aSIdo Barnea	 *       for n < 15, S[n] = S[(n:0) | (350:350 - (14 - n))]
828a551c94aSIdo Barnea	 *
829a551c94aSIdo Barnea	 *    To simplify for programming, the algorithm is implemented
830a551c94aSIdo Barnea	 *    in software this way:
831a551c94aSIdo Barnea	 *
832a551c94aSIdo Barnea	 *    key[31:0], hi_hash_dword[31:0], lo_hash_dword[31:0], hash[15:0]
833a551c94aSIdo Barnea	 *
834a551c94aSIdo Barnea	 *    for (i = 0; i < 352; i+=32)
835a551c94aSIdo Barnea	 *        hi_hash_dword[31:0] ^= Stream[(i+31):i];
836a551c94aSIdo Barnea	 *
837a551c94aSIdo Barnea	 *    lo_hash_dword[15:0]  ^= Stream[15:0];
838a551c94aSIdo Barnea	 *    lo_hash_dword[15:0]  ^= hi_hash_dword[31:16];
839a551c94aSIdo Barnea	 *    lo_hash_dword[31:16] ^= hi_hash_dword[15:0];
840a551c94aSIdo Barnea	 *
841a551c94aSIdo Barnea	 *    hi_hash_dword[31:0]  ^= Stream[351:320];
842a551c94aSIdo Barnea	 *
843a551c94aSIdo Barnea	 *    if (key[0])
844a551c94aSIdo Barnea	 *        hash[15:0] ^= Stream[15:0];
845a551c94aSIdo Barnea	 *
846a551c94aSIdo Barnea	 *    for (i = 0; i < 16; i++) {
847a551c94aSIdo Barnea	 *        if (key[i])
848a551c94aSIdo Barnea	 *            hash[15:0] ^= lo_hash_dword[(i+15):i];
849a551c94aSIdo Barnea	 *        if (key[i + 16])
850a551c94aSIdo Barnea	 *            hash[15:0] ^= hi_hash_dword[(i+15):i];
851a551c94aSIdo Barnea	 *    }
852a551c94aSIdo Barnea	 *
853a551c94aSIdo Barnea	 */
854a551c94aSIdo Barnea	__be32 common_hash_dword = 0;
855a551c94aSIdo Barnea	u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
856a551c94aSIdo Barnea	u32 hash_result = 0;
857a551c94aSIdo Barnea	u8 i;
858a551c94aSIdo Barnea
859a551c94aSIdo Barnea	/* record the flow_vm_vlan bits as they are a key part to the hash */
860a551c94aSIdo Barnea	flow_vm_vlan = IXGBE_NTOHL(atr_input->dword_stream[0]);
861a551c94aSIdo Barnea
862a551c94aSIdo Barnea	/* generate common hash dword */
863a551c94aSIdo Barnea	for (i = 1; i <= 13; i++)
864a551c94aSIdo Barnea		common_hash_dword ^= atr_input->dword_stream[i];
865a551c94aSIdo Barnea
866a551c94aSIdo Barnea	hi_hash_dword = IXGBE_NTOHL(common_hash_dword);
867a551c94aSIdo Barnea
868a551c94aSIdo Barnea	/* low dword is word swapped version of common */
869a551c94aSIdo Barnea	lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
870a551c94aSIdo Barnea
871a551c94aSIdo Barnea	/* apply flow ID/VM pool/VLAN ID bits to hash words */
872a551c94aSIdo Barnea	hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
873a551c94aSIdo Barnea
874a551c94aSIdo Barnea	/* Process bits 0 and 16 */
875a551c94aSIdo Barnea	if (key & 0x0001)
876a551c94aSIdo Barnea		hash_result ^= lo_hash_dword;
877a551c94aSIdo Barnea	if (key & 0x00010000)
878a551c94aSIdo Barnea		hash_result ^= hi_hash_dword;
879a551c94aSIdo Barnea
880a551c94aSIdo Barnea	/*
881a551c94aSIdo Barnea	 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
882a551c94aSIdo Barnea	 * delay this because bit 0 of the stream should not be processed
883a551c94aSIdo Barnea	 * so we do not add the vlan until after bit 0 was processed
884a551c94aSIdo Barnea	 */
885a551c94aSIdo Barnea	lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
886a551c94aSIdo Barnea
887a551c94aSIdo Barnea
888a551c94aSIdo Barnea	/* process the remaining 30 bits in the key 2 bits at a time */
889a551c94aSIdo Barnea	for (i = 15; i; i--) {
890a551c94aSIdo Barnea		if (key & (0x0001 << i))
891a551c94aSIdo Barnea			hash_result ^= lo_hash_dword >> i;
892a551c94aSIdo Barnea		if (key & (0x00010000 << i))
893a551c94aSIdo Barnea			hash_result ^= hi_hash_dword >> i;
894a551c94aSIdo Barnea	}
895a551c94aSIdo Barnea
896a551c94aSIdo Barnea	return hash_result;
897a551c94aSIdo Barnea}
898a551c94aSIdo Barnea
899a551c94aSIdo Barneastatic uint32_t
900a551c94aSIdo Barneaatr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
901a551c94aSIdo Barnea		enum rte_fdir_pballoc_type pballoc)
902a551c94aSIdo Barnea{
903a551c94aSIdo Barnea	if (pballoc == RTE_FDIR_PBALLOC_256K)
904a551c94aSIdo Barnea		return ixgbe_atr_compute_hash_82599(input,
905a551c94aSIdo Barnea				IXGBE_ATR_BUCKET_HASH_KEY) &
906a551c94aSIdo Barnea				PERFECT_BUCKET_256KB_HASH_MASK;
907a551c94aSIdo Barnea	else if (pballoc == RTE_FDIR_PBALLOC_128K)
908a551c94aSIdo Barnea		return ixgbe_atr_compute_hash_82599(input,
909a551c94aSIdo Barnea				IXGBE_ATR_BUCKET_HASH_KEY) &
910a551c94aSIdo Barnea				PERFECT_BUCKET_128KB_HASH_MASK;
911a551c94aSIdo Barnea	else
912a551c94aSIdo Barnea		return ixgbe_atr_compute_hash_82599(input,
913a551c94aSIdo Barnea				IXGBE_ATR_BUCKET_HASH_KEY) &
914a551c94aSIdo Barnea				PERFECT_BUCKET_64KB_HASH_MASK;
915a551c94aSIdo Barnea}
916a551c94aSIdo Barnea
917a551c94aSIdo Barnea/**
918a551c94aSIdo Barnea * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
919a551c94aSIdo Barnea * @hw: pointer to hardware structure
920a551c94aSIdo Barnea */
921a551c94aSIdo Barneastatic inline int
922a551c94aSIdo Barneaixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw, uint32_t *fdircmd)
923a551c94aSIdo Barnea{
924a551c94aSIdo Barnea	int i;
925a551c94aSIdo Barnea
926a551c94aSIdo Barnea	for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
927a551c94aSIdo Barnea		*fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
928a551c94aSIdo Barnea		if (!(*fdircmd & IXGBE_FDIRCMD_CMD_MASK))
929a551c94aSIdo Barnea			return 0;
930a551c94aSIdo Barnea		rte_delay_us(IXGBE_FDIRCMD_CMD_INTERVAL_US);
931a551c94aSIdo Barnea	}
932a551c94aSIdo Barnea
933a551c94aSIdo Barnea	return -ETIMEDOUT;
934a551c94aSIdo Barnea}
935a551c94aSIdo Barnea
936a551c94aSIdo Barnea/*
937a551c94aSIdo Barnea * Calculate the hash value needed for signature-match filters. In the FreeBSD
938a551c94aSIdo Barnea * driver, this is done by the optimised function
939a551c94aSIdo Barnea * ixgbe_atr_compute_sig_hash_82599(). However that can't be used here as it
940a551c94aSIdo Barnea * doesn't support calculating a hash for an IPv6 filter.
941a551c94aSIdo Barnea */
942a551c94aSIdo Barneastatic uint32_t
943a551c94aSIdo Barneaatr_compute_sig_hash_82599(union ixgbe_atr_input *input,
944a551c94aSIdo Barnea		enum rte_fdir_pballoc_type pballoc)
945a551c94aSIdo Barnea{
946a551c94aSIdo Barnea	uint32_t bucket_hash, sig_hash;
947a551c94aSIdo Barnea
948a551c94aSIdo Barnea	if (pballoc == RTE_FDIR_PBALLOC_256K)
949a551c94aSIdo Barnea		bucket_hash = ixgbe_atr_compute_hash_82599(input,
950a551c94aSIdo Barnea				IXGBE_ATR_BUCKET_HASH_KEY) &
951a551c94aSIdo Barnea				SIG_BUCKET_256KB_HASH_MASK;
952a551c94aSIdo Barnea	else if (pballoc == RTE_FDIR_PBALLOC_128K)
953a551c94aSIdo Barnea		bucket_hash = ixgbe_atr_compute_hash_82599(input,
954a551c94aSIdo Barnea				IXGBE_ATR_BUCKET_HASH_KEY) &
955a551c94aSIdo Barnea				SIG_BUCKET_128KB_HASH_MASK;
956a551c94aSIdo Barnea	else
957a551c94aSIdo Barnea		bucket_hash = ixgbe_atr_compute_hash_82599(input,
958a551c94aSIdo Barnea				IXGBE_ATR_BUCKET_HASH_KEY) &
959a551c94aSIdo Barnea				SIG_BUCKET_64KB_HASH_MASK;
960a551c94aSIdo Barnea
961a551c94aSIdo Barnea	sig_hash = ixgbe_atr_compute_hash_82599(input,
962a551c94aSIdo Barnea			IXGBE_ATR_SIGNATURE_HASH_KEY);
963a551c94aSIdo Barnea
964a551c94aSIdo Barnea	return (sig_hash << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT) | bucket_hash;
965a551c94aSIdo Barnea}
966a551c94aSIdo Barnea
967a551c94aSIdo Barnea/*
968a551c94aSIdo Barnea * This is based on ixgbe_fdir_write_perfect_filter_82599() in
969a551c94aSIdo Barnea * base/ixgbe_82599.c, with the ability to set extra flags in FDIRCMD register
970a551c94aSIdo Barnea * added, and IPv6 support also added. The hash value is also pre-calculated
971a551c94aSIdo Barnea * as the pballoc value is needed to do it.
972a551c94aSIdo Barnea */
973a551c94aSIdo Barneastatic int
974a551c94aSIdo Barneafdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
975a551c94aSIdo Barnea			union ixgbe_atr_input *input, uint8_t queue,
976a551c94aSIdo Barnea			uint32_t fdircmd, uint32_t fdirhash,
977a551c94aSIdo Barnea			enum rte_fdir_mode mode)
978a551c94aSIdo Barnea{
979a551c94aSIdo Barnea	uint32_t fdirport, fdirvlan;
980a551c94aSIdo Barnea	u32 addr_low, addr_high;
981a551c94aSIdo Barnea	u32 tunnel_type = 0;
982a551c94aSIdo Barnea	int err = 0;
983a551c94aSIdo Barnea	volatile uint32_t *reg;
984a551c94aSIdo Barnea
985a551c94aSIdo Barnea	if (mode == RTE_FDIR_MODE_PERFECT) {
986a551c94aSIdo Barnea		/* record the IPv4 address (big-endian)
987a551c94aSIdo Barnea		 * can not use IXGBE_WRITE_REG.
988a551c94aSIdo Barnea		 */
989a551c94aSIdo Barnea		reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPSA);
990a551c94aSIdo Barnea		*reg = input->formatted.src_ip[0];
991a551c94aSIdo Barnea		reg = IXGBE_PCI_REG_ADDR(hw, IXGBE_FDIRIPDA);
992a551c94aSIdo Barnea		*reg = input->formatted.dst_ip[0];
993a551c94aSIdo Barnea
994a551c94aSIdo Barnea		/* record source and destination port (little-endian)*/
995a551c94aSIdo Barnea		fdirport = IXGBE_NTOHS(input->formatted.dst_port);
996a551c94aSIdo Barnea		fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
997a551c94aSIdo Barnea		fdirport |= IXGBE_NTOHS(input->formatted.src_port);
998a551c94aSIdo Barnea		IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
999a551c94aSIdo Barnea	} else if (mode >= RTE_FDIR_MODE_PERFECT_MAC_VLAN &&
1000a551c94aSIdo Barnea		   mode <= RTE_FDIR_MODE_PERFECT_TUNNEL) {
1001a551c94aSIdo Barnea		/* for mac vlan and tunnel modes */
1002a551c94aSIdo Barnea		addr_low = ((u32)input->formatted.inner_mac[0] |
1003a551c94aSIdo Barnea			    ((u32)input->formatted.inner_mac[1] << 8) |
1004a551c94aSIdo Barnea			    ((u32)input->formatted.inner_mac[2] << 16) |
1005a551c94aSIdo Barnea			    ((u32)input->formatted.inner_mac[3] << 24));
1006a551c94aSIdo Barnea		addr_high = ((u32)input->formatted.inner_mac[4] |
1007a551c94aSIdo Barnea			     ((u32)input->formatted.inner_mac[5] << 8));
1008a551c94aSIdo Barnea
1009a551c94aSIdo Barnea		if (mode == RTE_FDIR_MODE_PERFECT_MAC_VLAN) {
1010a551c94aSIdo Barnea			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1011a551c94aSIdo Barnea			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), addr_high);
1012a551c94aSIdo Barnea			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2), 0);
1013a551c94aSIdo Barnea		} else {
1014a551c94aSIdo Barnea			/* tunnel mode */
1015a551c94aSIdo Barnea			if (input->formatted.tunnel_type !=
1016a551c94aSIdo Barnea				RTE_FDIR_TUNNEL_TYPE_NVGRE)
1017a551c94aSIdo Barnea				tunnel_type = 0x80000000;
1018a551c94aSIdo Barnea			tunnel_type |= addr_high;
1019a551c94aSIdo Barnea			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(0), addr_low);
1020a551c94aSIdo Barnea			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(1), tunnel_type);
1021a551c94aSIdo Barnea			IXGBE_WRITE_REG(hw, IXGBE_FDIRSIPv6(2),
1022a551c94aSIdo Barnea					input->formatted.tni_vni);
1023a551c94aSIdo Barnea		}
1024a551c94aSIdo Barnea	}
1025a551c94aSIdo Barnea
1026a551c94aSIdo Barnea	/* record vlan (little-endian) and flex_bytes(big-endian) */
1027a551c94aSIdo Barnea	fdirvlan = input->formatted.flex_bytes;
1028a551c94aSIdo Barnea	fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1029a551c94aSIdo Barnea	fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1030a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1031a551c94aSIdo Barnea
1032a551c94aSIdo Barnea	/* configure FDIRHASH register */
1033a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1034a551c94aSIdo Barnea
1035a551c94aSIdo Barnea	/*
1036a551c94aSIdo Barnea	 * flush all previous writes to make certain registers are
1037a551c94aSIdo Barnea	 * programmed prior to issuing the command
1038a551c94aSIdo Barnea	 */
1039a551c94aSIdo Barnea	IXGBE_WRITE_FLUSH(hw);
1040a551c94aSIdo Barnea
1041a551c94aSIdo Barnea	/* configure FDIRCMD register */
1042a551c94aSIdo Barnea	fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1044a551c94aSIdo Barnea	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1045a551c94aSIdo Barnea	fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1046a551c94aSIdo Barnea	fdircmd |= (uint32_t)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1047a551c94aSIdo Barnea
1048a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1049a551c94aSIdo Barnea
1050a551c94aSIdo Barnea	PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1051a551c94aSIdo Barnea
1052a551c94aSIdo Barnea	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1053a551c94aSIdo Barnea	if (err < 0)
1054a551c94aSIdo Barnea		PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1055a551c94aSIdo Barnea
1056a551c94aSIdo Barnea	return err;
1057a551c94aSIdo Barnea}
1058a551c94aSIdo Barnea
1059a551c94aSIdo Barnea/**
1060a551c94aSIdo Barnea * This function is based on ixgbe_atr_add_signature_filter_82599() in
1061a551c94aSIdo Barnea * base/ixgbe_82599.c, but uses a pre-calculated hash value. It also supports
1062a551c94aSIdo Barnea * setting extra fields in the FDIRCMD register, and removes the code that was
1063a551c94aSIdo Barnea * verifying the flow_type field. According to the documentation, a flow type of
1064a551c94aSIdo Barnea * 00 (i.e. not TCP, UDP, or SCTP) is not supported, however it appears to
1065a551c94aSIdo Barnea * work ok...
1066a551c94aSIdo Barnea *
1067a551c94aSIdo Barnea *  Adds a signature hash filter
1068a551c94aSIdo Barnea *  @hw: pointer to hardware structure
1069a551c94aSIdo Barnea *  @input: unique input dword
1070a551c94aSIdo Barnea *  @queue: queue index to direct traffic to
1071a551c94aSIdo Barnea *  @fdircmd: any extra flags to set in fdircmd register
1072a551c94aSIdo Barnea *  @fdirhash: pre-calculated hash value for the filter
1073a551c94aSIdo Barnea **/
1074a551c94aSIdo Barneastatic int
1075a551c94aSIdo Barneafdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1076a551c94aSIdo Barnea		union ixgbe_atr_input *input, u8 queue, uint32_t fdircmd,
1077a551c94aSIdo Barnea		uint32_t fdirhash)
1078a551c94aSIdo Barnea{
1079a551c94aSIdo Barnea	int err = 0;
1080a551c94aSIdo Barnea
1081a551c94aSIdo Barnea	PMD_INIT_FUNC_TRACE();
1082a551c94aSIdo Barnea
1083a551c94aSIdo Barnea	/* configure FDIRCMD register */
1084a551c94aSIdo Barnea	fdircmd |= IXGBE_FDIRCMD_CMD_ADD_FLOW |
1086a551c94aSIdo Barnea	fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1087a551c94aSIdo Barnea	fdircmd |= (uint32_t)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1088a551c94aSIdo Barnea
1089a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1090a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1091a551c94aSIdo Barnea
1092a551c94aSIdo Barnea	PMD_DRV_LOG(DEBUG, "Rx Queue=%x hash=%x", queue, fdirhash);
1093a551c94aSIdo Barnea
1094a551c94aSIdo Barnea	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1095a551c94aSIdo Barnea	if (err < 0)
1096a551c94aSIdo Barnea		PMD_DRV_LOG(ERR, "Timeout writing flow director filter.");
1097a551c94aSIdo Barnea
1098a551c94aSIdo Barnea	return err;
1099a551c94aSIdo Barnea}
1100a551c94aSIdo Barnea
1101a551c94aSIdo Barnea/*
1102a551c94aSIdo Barnea * This is based on ixgbe_fdir_erase_perfect_filter_82599() in
1103a551c94aSIdo Barnea * base/ixgbe_82599.c. It is modified to take in the hash as a parameter so
1104a551c94aSIdo Barnea * that it can be used for removing signature and perfect filters.
1105a551c94aSIdo Barnea */
1106a551c94aSIdo Barneastatic int
1107a551c94aSIdo Barneafdir_erase_filter_82599(struct ixgbe_hw *hw, uint32_t fdirhash)
1108a551c94aSIdo Barnea{
1109a551c94aSIdo Barnea	uint32_t fdircmd = 0;
1110a551c94aSIdo Barnea	int err = 0;
1111a551c94aSIdo Barnea
1112a551c94aSIdo Barnea	IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1113a551c94aSIdo Barnea
1114a551c94aSIdo Barnea	/* flush hash to HW */
1115a551c94aSIdo Barnea	IXGBE_WRITE_FLUSH(hw);
1116a551c94aSIdo Barnea
1117a551c94aSIdo Barnea	/* Query if filter is present */
1119a551c94aSIdo Barnea
1120a551c94aSIdo Barnea	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1121a551c94aSIdo Barnea	if (err < 0) {
1122a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "Timeout querying for flow director filter.");
1123a551c94aSIdo Barnea		return err;
1124a551c94aSIdo Barnea	}
1125a551c94aSIdo Barnea
1126a551c94aSIdo Barnea	/* if filter exists in hardware then remove it */
1127a551c94aSIdo Barnea	if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1128a551c94aSIdo Barnea		IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1129a551c94aSIdo Barnea		IXGBE_WRITE_FLUSH(hw);
1130a551c94aSIdo Barnea		IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1131a551c94aSIdo Barnea				IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1132a551c94aSIdo Barnea	}
1133a551c94aSIdo Barnea	err = ixgbe_fdir_check_cmd_complete(hw, &fdircmd);
1134a551c94aSIdo Barnea	if (err < 0)
1135a551c94aSIdo Barnea		PMD_INIT_LOG(ERR, "Timeout erasing flow director filter.");
1136a551c94aSIdo Barnea	return err;
1137a551c94aSIdo Barnea
1138a551c94aSIdo Barnea}
1139a551c94aSIdo Barnea
11409ca4a157SIdo Barneastatic inline struct ixgbe_fdir_filter *
11419ca4a157SIdo Barneaixgbe_fdir_filter_lookup(struct ixgbe_hw_fdir_info *fdir_info,
11429ca4a157SIdo Barnea			 union ixgbe_atr_input *key)
11439ca4a157SIdo Barnea{
11449ca4a157SIdo Barnea	int ret;
11459ca4a157SIdo Barnea
11469ca4a157SIdo Barnea	ret = rte_hash_lookup(fdir_info->hash_handle, (const void *)key);
11479ca4a157SIdo Barnea	if (ret < 0)
11489ca4a157SIdo Barnea		return NULL;
11499ca4a157SIdo Barnea
11509ca4a157SIdo Barnea	return fdir_info->hash_map[ret];
11519ca4a157SIdo Barnea}
11529ca4a157SIdo Barnea
11539ca4a157SIdo Barneastatic inline int
11549ca4a157SIdo Barneaixgbe_insert_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
11559ca4a157SIdo Barnea			 struct ixgbe_fdir_filter *fdir_filter)
11569ca4a157SIdo Barnea{
11579ca4a157SIdo Barnea	int ret;
11589ca4a157SIdo Barnea
11599ca4a157SIdo Barnea	ret = rte_hash_add_key(fdir_info->hash_handle,
11609ca4a157SIdo Barnea			       &fdir_filter->ixgbe_fdir);
11619ca4a157SIdo Barnea
11629ca4a157SIdo Barnea	if (ret < 0) {
11639ca4a157SIdo Barnea		PMD_DRV_LOG(ERR,
11649ca4a157SIdo Barnea			    "Failed to insert fdir filter to hash table %d!",
11659ca4a157SIdo Barnea			    ret);
11669ca4a157SIdo Barnea		return ret;
11679ca4a157SIdo Barnea	}
11689ca4a157SIdo Barnea
11699ca4a157SIdo Barnea	fdir_info->hash_map[ret] = fdir_filter;
11709ca4a157SIdo Barnea
11719ca4a157SIdo Barnea	TAILQ_INSERT_TAIL(&fdir_info->fdir_list, fdir_filter, entries);
11729ca4a157SIdo Barnea
11739ca4a157SIdo Barnea	return 0;
11749ca4a157SIdo Barnea}
11759ca4a157SIdo Barnea
11769ca4a157SIdo Barneastatic inline int
11779ca4a157SIdo Barneaixgbe_remove_fdir_filter(struct ixgbe_hw_fdir_info *fdir_info,
11789ca4a157SIdo Barnea			 union ixgbe_atr_input *key)
11799ca4a157SIdo Barnea{
11809ca4a157SIdo Barnea	int ret;
11819ca4a157SIdo Barnea	struct ixgbe_fdir_filter *fdir_filter;
11829ca4a157SIdo Barnea
11839ca4a157SIdo Barnea	ret = rte_hash_del_key(fdir_info->hash_handle, key);
11849ca4a157SIdo Barnea
11859ca4a157SIdo Barnea	if (ret < 0) {
11869ca4a157SIdo Barnea		PMD_DRV_LOG(ERR, "No such fdir filter to delete %d!", ret);
11879ca4a157SIdo Barnea		return ret;
11889ca4a157SIdo Barnea	}
11899ca4a157SIdo Barnea
11909ca4a157SIdo Barnea	fdir_filter = fdir_info->hash_map[ret];
11919ca4a157SIdo Barnea	fdir_info->hash_map[ret] = NULL;
11929ca4a157SIdo Barnea
11939ca4a157SIdo Barnea	TAILQ_REMOVE(&fdir_info->fdir_list, fdir_filter, entries);
11949ca4a157SIdo Barnea	rte_free(fdir_filter);
11959ca4a157SIdo Barnea
11969ca4a157SIdo Barnea	return 0;
11979ca4a157SIdo Barnea}
11989ca4a157SIdo Barnea
1199a551c94aSIdo Barneastatic int
12009ca4a157SIdo Barneaixgbe_interpret_fdir_filter(struct rte_eth_dev *dev,
12019ca4a157SIdo Barnea			    const struct rte_eth_fdir_filter *fdir_filter,
12029ca4a157SIdo Barnea			    struct ixgbe_fdir_rule *rule)
12039ca4a157SIdo Barnea{
12049ca4a157SIdo Barnea	enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
12059ca4a157SIdo Barnea	int err;
12069ca4a157SIdo Barnea
12079ca4a157SIdo Barnea	memset(rule, 0, sizeof(struct ixgbe_fdir_rule));
12089ca4a157SIdo Barnea
12099ca4a157SIdo Barnea	err = ixgbe_fdir_filter_to_atr_input(fdir_filter,
12109ca4a157SIdo Barnea					     &rule->ixgbe_fdir,
12119ca4a157SIdo Barnea					     fdir_mode);
12129ca4a157SIdo Barnea	if (err)
12139ca4a157SIdo Barnea		return err;
12149ca4a157SIdo Barnea
12159ca4a157SIdo Barnea	rule->mode = fdir_mode;
12169ca4a157SIdo Barnea	if (fdir_filter->action.behavior == RTE_ETH_FDIR_REJECT)
12179ca4a157SIdo Barnea		rule->fdirflags = IXGBE_FDIRCMD_DROP;
12189ca4a157SIdo Barnea	rule->queue = fdir_filter->action.rx_queue;
12199ca4a157SIdo Barnea	rule->soft_id = fdir_filter->soft_id;
12209ca4a157SIdo Barnea
12219ca4a157SIdo Barnea	return 0;
12229ca4a157SIdo Barnea}
12239ca4a157SIdo Barnea
12249ca4a157SIdo Barneaint
12259ca4a157SIdo Barneaixgbe_fdir_filter_program(struct rte_eth_dev *dev,
12269ca4a157SIdo Barnea			  struct ixgbe_fdir_rule *rule,
1227a551c94aSIdo Barnea			  bool del,
1228a551c94aSIdo Barnea			  bool update)
1229a551c94aSIdo Barnea{
1230a551c94aSIdo Barnea	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1231a551c94aSIdo Barnea	uint32_t fdircmd_flags;
1232a551c94aSIdo Barnea	uint32_t fdirhash;
1233a551c94aSIdo Barnea	uint8_t queue;
1234a551c94aSIdo Barnea	bool is_perfect = FALSE;
1235a551c94aSIdo Barnea	int err;
1236a551c94aSIdo Barnea	struct ixgbe_hw_fdir_info *info =
1237a551c94aSIdo Barnea		IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->data->dev_private);
1238a551c94aSIdo Barnea	enum rte_fdir_mode fdir_mode = dev->data->dev_conf.fdir_conf.mode;
12399ca4a157SIdo Barnea	struct ixgbe_fdir_filter *node;
12409ca4a157SIdo Barnea	bool add_node = FALSE;
1241a551c94aSIdo Barnea
12429ca4a157SIdo Barnea	if (fdir_mode == RTE_FDIR_MODE_NONE ||
12439ca4a157SIdo Barnea	    fdir_mode != rule->mode)
1244a551c94aSIdo Barnea		return -ENOTSUP;
1245a551c94aSIdo Barnea
1246a551c94aSIdo Barnea	/*
1247a551c94aSIdo Barnea	 * Sanity check for x550.
1248a551c94aSIdo Barnea	 * When adding a new filter with flow type set to IPv4-other,
1249a551c94aSIdo Barnea	 * the flow director mask should be configed before,
1250a551c94aSIdo Barnea	 * and the L4 protocol and ports are masked.
1251a551c94aSIdo Barnea	 */
1252a551c94aSIdo Barnea	if ((!del) &&
1253a551c94aSIdo Barnea	    (hw->mac.type == ixgbe_mac_X550 ||
1254a551c94aSIdo Barnea	     hw->mac.type == ixgbe_mac_X550EM_x ||
1255a551c94aSIdo Barnea	     hw->mac.type == ixgbe_mac_X550EM_a) &&
12569ca4a157SIdo Barnea	    (rule->ixgbe_fdir.formatted.flow_type ==
1257a551c94aSIdo Barnea	     RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) &&
1258a551c94aSIdo Barnea	    (info->mask.src_port_mask != 0 ||
1259a551c94aSIdo Barnea	     info->mask.dst_port_mask != 0)) {
1260a551c94aSIdo Barnea		PMD_DRV_LOG(ERR, "By this device,"
1261a551c94aSIdo Barnea			    " IPv4-other is not supported without"
1262a551c94aSIdo Barnea			    " L4 protocol and ports masked!");
1263a551c94aSIdo Barnea		return -ENOTSUP;
1264a551c94aSIdo Barnea	}
1265a551c94aSIdo Barnea
1266a551c94aSIdo Barnea	if (fdir_mode >= RTE_FDIR_MODE_PERFECT &&
1267a551c94aSIdo Barnea	    fdir_mode <= RTE_FDIR_MODE_PERFECT_TUNNEL)
1268a551c94aSIdo Barnea		is_perfect = TRUE;
1269a551c94aSIdo Barnea
1270a551c94aSIdo Barnea	if (is_perfect) {
12713c0de05aSIdo Barnea#ifndef TREX_PATCH
12723c0de05aSIdo Barnea        // No reason not to use IPV6 in perfect filters. It is working.
12739ca4a157SIdo Barnea		if (rule->ixgbe_fdir.formatted.flow_type &
12749ca4a157SIdo Barnea		    IXGBE_ATR_L4TYPE_IPV6_MASK) {
1275a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, "IPv6 is not supported in"
1276a551c94aSIdo Barnea				    " perfect mode!");
1277a551c94aSIdo Barnea			return -ENOTSUP;
1278a551c94aSIdo Barnea		}
12793c0de05aSIdo Barnea#endif
12809ca4a157SIdo Barnea		fdirhash = atr_compute_perfect_hash_82599(&rule->ixgbe_fdir,
1281a551c94aSIdo Barnea							  dev->data->dev_conf.fdir_conf.pballoc);
12829ca4a157SIdo Barnea		fdirhash |= rule->soft_id <<
1284a551c94aSIdo Barnea	} else
12859ca4a157SIdo Barnea		fdirhash = atr_compute_sig_hash_82599(&rule->ixgbe_fdir,
1286a551c94aSIdo Barnea						      dev->data->dev_conf.fdir_conf.pballoc);
1287a551c94aSIdo Barnea
1288a551c94aSIdo Barnea	if (del) {
12899ca4a157SIdo Barnea		err = ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
12909ca4a157SIdo Barnea		if (err < 0)
12919ca4a157SIdo Barnea			return err;
12929ca4a157SIdo Barnea
1293a551c94aSIdo Barnea		err = fdir_erase_filter_82599(hw, fdirhash);
1294a551c94aSIdo Barnea		if (err < 0)
1295a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, "Fail to delete FDIR filter!");
1296a551c94aSIdo Barnea		else
1297a551c94aSIdo Barnea			PMD_DRV_LOG(DEBUG, "Success to delete FDIR filter!");
1298a551c94aSIdo Barnea		return err;
1299a551c94aSIdo Barnea	}
1300a551c94aSIdo Barnea	/* add or update an fdir filter*/
1301a551c94aSIdo Barnea	fdircmd_flags = (update) ? IXGBE_FDIRCMD_FILTER_UPDATE : 0;
13029ca4a157SIdo Barnea	if (rule->fdirflags & IXGBE_FDIRCMD_DROP) {
1303a551c94aSIdo Barnea		if (is_perfect) {
1304a551c94aSIdo Barnea			queue = dev->data->dev_conf.fdir_conf.drop_queue;
1305a551c94aSIdo Barnea			fdircmd_flags |= IXGBE_FDIRCMD_DROP;
1306a551c94aSIdo Barnea		} else {
1307a551c94aSIdo Barnea			PMD_DRV_LOG(ERR, "Drop option is not supported in"
1308a551c94aSIdo Barnea				    " signature mode.");
1309a551c94aSIdo Barnea			return -EINVAL;
1310a551c94aSIdo Barnea		}
13119ca4a157SIdo Barnea	} else if (rule->queue < IXGBE_MAX_RX_QUEUE_NUM)
13129ca4a157SIdo Barnea		queue = (uint8_t)rule->queue;
1313a551c94aSIdo Barnea	else
1314a551c94aSIdo Barnea		return -EINVAL;
1315a551c94aSIdo Barnea
13169ca4a157SIdo Barnea	node = ixgbe_fdir_filter_lookup(info, &rule->ixgbe_fdir);
13179ca4a157SIdo Barnea	if (node) {
13189ca4a157SIdo Barnea		if (update) {
13199ca4a157SIdo Barnea			node->fdirflags = fdircmd_flags;
13209ca4a157SIdo Barnea			node->fdirhash = fdirhash;
13219ca4a157SIdo Barnea			node->queue = queue;
13229ca4a157SIdo Barnea		} else {
13239ca4a157SIdo Barnea			PMD_DRV_LOG(ERR, "Conflict with existing fdir filter!");
13249ca4a157SIdo Barnea			return -EINVAL;
13259ca4a157SIdo Barnea		}
13269ca4a157SIdo Barnea	} else {
13279ca4a157SIdo Barnea		add_node = TRUE;
13289ca4a157SIdo Barnea		node = rte_zmalloc("ixgbe_fdir",
13299ca4a157SIdo Barnea				   sizeof(struct ixgbe_fdir_filter),
13309ca4a157SIdo Barnea				   0);
13319ca4a157SIdo Barnea		if (!node)
13329ca4a157SIdo Barnea			return -ENOMEM;
13339ca4a157SIdo Barnea		(void)rte_memcpy(&node->ixgbe_fdir,
13349ca4a157SIdo Barnea				 &rule->ixgbe_fdir,
13359ca4a157SIdo Barnea				 sizeof(union ixgbe_atr_input));
13369ca4a157SIdo Barnea		node->fdirflags = fdircmd_flags;
13379ca4a157SIdo Barnea		node->fdirhash = fdirhash;
13389ca4a157SIdo Barnea		node->queue = queue;
13399ca4a157SIdo Barnea
13409ca4a157SIdo Barnea		err = ixgbe_insert_fdir_filter(info, node);
13419ca4a157SIdo Barnea		if (err < 0) {
13429ca4a157SIdo Barnea			rte_free(node);
13439ca4a157SIdo Barnea			return err;
13449ca4a157SIdo Barnea		}
13459ca4a157SIdo Barnea	}
13469ca4a157SIdo Barnea
1347a551c94aSIdo Barnea	if (is_perfect) {
13489ca4a157SIdo Barnea		err = fdir_write_perfect_filter_82599(hw, &rule->ixgbe_fdir,
13499ca4a157SIdo Barnea						      queue, fdircmd_flags,
13509ca4a157SIdo Barnea						      fdirhash, fdir_mode);
1351a551c94aSIdo Barnea	} else {
13529ca4a157SIdo Barnea		err = fdir_add_signature_filter_82599(hw, &rule->ixgbe_fdir,
13539ca4a157SIdo Barnea						      queue, fdircmd_flags,
13549ca4a157SIdo Barnea						      fdirhash);
1355a551c94aSIdo Barnea	}
13569ca4a157SIdo Barnea	if (err < 0) {
1357a551c94aSIdo Barnea		PMD_DRV_LOG(ERR, "Fail to add FDIR filter!");
13589ca4a157SIdo Barnea
13599ca4a157SIdo Barnea		if (add_node)
13609ca4a157SIdo Barnea			(void)ixgbe_remove_fdir_filter(info, &rule->ixgbe_fdir);
13619ca4a157SIdo Barnea	} else {
1362a551c94aSIdo Barnea		PMD_DRV_LOG(DEBUG, "Success to add FDIR filter");
13639ca4a157SIdo Barnea	}
1364a551c94aSIdo Barnea
1365a551c94aSIdo Barnea	return err;
1366a551c94aSIdo Barnea}
1367a551c94aSIdo Barnea
13689ca4a157SIdo Barnea/* ixgbe_add_del_fdir_filter - add or remove a flow diretor filter.
13699ca4a157SIdo Barnea * @dev: pointer to the structure rte_eth_dev
13709ca4a157SIdo Barnea * @fdir_filter: fdir filter entry
13719ca4a157SIdo Barnea * @del: 1 - delete, 0 - add
13729ca4a157SIdo Barnea * @update: 1 - update
13739ca4a157SIdo Barnea */
13749ca4a157SIdo Barneastatic int
13759ca4a157SIdo Barneaixgbe_add_del_fdir_filter(struct rte_eth_dev *dev,
13769ca4a157SIdo Barnea			  const struct rte_eth_fdir_filter *fdir_filter,
13779ca4a157SIdo Barnea			  bool del,
13789ca4a157SIdo Barnea			  bool update)
13799ca4a157SIdo Barnea{
13809ca4a157SIdo Barnea	struct ixgbe_fdir_rule rule;
13819ca4a157SIdo Barnea	int err;
13829ca4a157SIdo Barnea
13839ca4a157SIdo Barnea	err = ixgbe_interpret_fdir_filter(dev, fdir_filter, &rule);
13849ca4a157SIdo Barnea
13859ca4a157SIdo Barnea	if (err)
13869ca4a157SIdo Barnea		return err;
13879ca4a157SIdo Barnea
13889ca4a157SIdo Barnea	return ixgbe_fdir_filter_program(dev, &rule, del, update);
13899ca4a157SIdo Barnea}
13909ca4a157SIdo Barnea
1391a551c94aSIdo Barneastatic int
1392a551c94aSIdo Barneaixgbe_fdir_flush(struct rte_eth_dev *dev)
1393a551c94aSIdo Barnea{
1394a551c94aSIdo Barnea	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1395a551c94aSIdo Barnea	struct ixgbe_hw_fdir_info *info =
1396a551c94aSIdo Barnea			IXGBE_DEV_PRIVATE_TO_FDIR_INFO(dev->