ixgbe_pf.c revision 9ca4a157
1/*-
2 *   BSD LICENSE
3 *
4 *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
5 *   All rights reserved.
6 *
7 *   Redistribution and use in source and binary forms, with or without
8 *   modification, are permitted provided that the following conditions
9 *   are met:
10 *
11 *     * Redistributions of source code must retain the above copyright
12 *       notice, this list of conditions and the following disclaimer.
13 *     * Redistributions in binary form must reproduce the above copyright
14 *       notice, this list of conditions and the following disclaimer in
15 *       the documentation and/or other materials provided with the
16 *       distribution.
17 *     * Neither the name of Intel Corporation nor the names of its
18 *       contributors may be used to endorse or promote products derived
19 *       from this software without specific prior written permission.
20 *
21 *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <stdio.h>
35#include <errno.h>
36#include <stdint.h>
37#include <stdlib.h>
38#include <unistd.h>
39#include <stdarg.h>
40#include <inttypes.h>
41
42#include <rte_interrupts.h>
43#include <rte_log.h>
44#include <rte_debug.h>
45#include <rte_eal.h>
46#include <rte_ether.h>
47#include <rte_ethdev.h>
48#include <rte_memcpy.h>
49#include <rte_malloc.h>
50#include <rte_random.h>
51
52#include "base/ixgbe_common.h"
53#include "ixgbe_ethdev.h"
54#include "rte_pmd_ixgbe.h"
55
56#define IXGBE_MAX_VFTA     (128)
57#define IXGBE_VF_MSG_SIZE_DEFAULT 1
58#define IXGBE_VF_GET_QUEUE_MSG_SIZE 5
59#define IXGBE_ETHERTYPE_FLOW_CTRL 0x8808
60
61static inline uint16_t
62dev_num_vf(struct rte_eth_dev *eth_dev)
63{
64	struct rte_pci_device *pci_dev = IXGBE_DEV_TO_PCI(eth_dev);
65
66	return pci_dev->max_vfs;
67}
68
69static inline
70int ixgbe_vf_perm_addr_gen(struct rte_eth_dev *dev, uint16_t vf_num)
71{
72	unsigned char vf_mac_addr[ETHER_ADDR_LEN];
73	struct ixgbe_vf_info *vfinfo =
74		*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
75	uint16_t vfn;
76
77	for (vfn = 0; vfn < vf_num; vfn++) {
78		eth_random_addr(vf_mac_addr);
79		/* keep the random address as default */
80		memcpy(vfinfo[vfn].vf_mac_addresses, vf_mac_addr,
81			   ETHER_ADDR_LEN);
82	}
83
84	return 0;
85}
86
87static inline int
88ixgbe_mb_intr_setup(struct rte_eth_dev *dev)
89{
90	struct ixgbe_interrupt *intr =
91		IXGBE_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
92
93	intr->mask |= IXGBE_EICR_MAILBOX;
94
95	return 0;
96}
97
98void ixgbe_pf_host_init(struct rte_eth_dev *eth_dev)
99{
100	struct ixgbe_vf_info **vfinfo =
101		IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
102	struct ixgbe_mirror_info *mirror_info =
103	IXGBE_DEV_PRIVATE_TO_PFDATA(eth_dev->data->dev_private);
104	struct ixgbe_uta_info *uta_info =
105	IXGBE_DEV_PRIVATE_TO_UTA(eth_dev->data->dev_private);
106	struct ixgbe_hw *hw =
107		IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
108	uint16_t vf_num;
109	uint8_t nb_queue;
110
111	PMD_INIT_FUNC_TRACE();
112
113	RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
114	vf_num = dev_num_vf(eth_dev);
115	if (vf_num == 0)
116		return;
117
118	*vfinfo = rte_zmalloc("vf_info", sizeof(struct ixgbe_vf_info) * vf_num, 0);
119	if (*vfinfo == NULL)
120		rte_panic("Cannot allocate memory for private VF data\n");
121
122	memset(mirror_info, 0, sizeof(struct ixgbe_mirror_info));
123	memset(uta_info, 0, sizeof(struct ixgbe_uta_info));
124	hw->mac.mc_filter_type = 0;
125
126	if (vf_num >= ETH_32_POOLS) {
127		nb_queue = 2;
128		RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_64_POOLS;
129	} else if (vf_num >= ETH_16_POOLS) {
130		nb_queue = 4;
131		RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_32_POOLS;
132	} else {
133		nb_queue = 8;
134		RTE_ETH_DEV_SRIOV(eth_dev).active = ETH_16_POOLS;
135	}
136
137	RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = nb_queue;
138	RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = vf_num;
139	RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = (uint16_t)(vf_num * nb_queue);
140
141	ixgbe_vf_perm_addr_gen(eth_dev, vf_num);
142
143	/* init_mailbox_params */
144	hw->mbx.ops.init_params(hw);
145
146	/* set mb interrupt mask */
147	ixgbe_mb_intr_setup(eth_dev);
148}
149
150void ixgbe_pf_host_uninit(struct rte_eth_dev *eth_dev)
151{
152	struct ixgbe_vf_info **vfinfo;
153	uint16_t vf_num;
154
155	PMD_INIT_FUNC_TRACE();
156
157	vfinfo = IXGBE_DEV_PRIVATE_TO_P_VFDATA(eth_dev->data->dev_private);
158
159	RTE_ETH_DEV_SRIOV(eth_dev).active = 0;
160	RTE_ETH_DEV_SRIOV(eth_dev).nb_q_per_pool = 0;
161	RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx = 0;
162	RTE_ETH_DEV_SRIOV(eth_dev).def_pool_q_idx = 0;
163
164	vf_num = dev_num_vf(eth_dev);
165	if (vf_num == 0)
166		return;
167
168	rte_free(*vfinfo);
169	*vfinfo = NULL;
170}
171
172static void
173ixgbe_add_tx_flow_control_drop_filter(struct rte_eth_dev *eth_dev)
174{
175	struct ixgbe_hw *hw =
176		IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
177	struct ixgbe_filter_info *filter_info =
178		IXGBE_DEV_PRIVATE_TO_FILTER_INFO(eth_dev->data->dev_private);
179	uint16_t vf_num;
180	int i;
181	struct ixgbe_ethertype_filter ethertype_filter;
182
183	if (!hw->mac.ops.set_ethertype_anti_spoofing) {
184		RTE_LOG(INFO, PMD, "ether type anti-spoofing is not"
185			" supported.\n");
186		return;
187	}
188
189	i = ixgbe_ethertype_filter_lookup(filter_info,
190					  IXGBE_ETHERTYPE_FLOW_CTRL);
191	if (i >= 0) {
192		RTE_LOG(ERR, PMD, "A ether type filter"
193			" entity for flow control already exists!\n");
194		return;
195	}
196
197	ethertype_filter.ethertype = IXGBE_ETHERTYPE_FLOW_CTRL;
198	ethertype_filter.etqf = IXGBE_ETQF_FILTER_EN |
199				IXGBE_ETQF_TX_ANTISPOOF |
200				IXGBE_ETHERTYPE_FLOW_CTRL;
201	ethertype_filter.etqs = 0;
202	ethertype_filter.conf = TRUE;
203	i = ixgbe_ethertype_filter_insert(filter_info,
204					  &ethertype_filter);
205	if (i < 0) {
206		RTE_LOG(ERR, PMD, "Cannot find an unused ether type filter"
207			" entity for flow control.\n");
208		return;
209	}
210
211	IXGBE_WRITE_REG(hw, IXGBE_ETQF(i),
212			(IXGBE_ETQF_FILTER_EN |
213			IXGBE_ETQF_TX_ANTISPOOF |
214			IXGBE_ETHERTYPE_FLOW_CTRL));
215
216	vf_num = dev_num_vf(eth_dev);
217	for (i = 0; i < vf_num; i++)
218		hw->mac.ops.set_ethertype_anti_spoofing(hw, true, i);
219}
220
221int ixgbe_pf_host_configure(struct rte_eth_dev *eth_dev)
222{
223	uint32_t vtctl, fcrth;
224	uint32_t vfre_slot, vfre_offset;
225	uint16_t vf_num;
226	const uint8_t VFRE_SHIFT = 5;  /* VFRE 32 bits per slot */
227	const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
228	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
229	uint32_t gpie, gcr_ext;
230	uint32_t vlanctrl;
231	int i;
232
233	vf_num = dev_num_vf(eth_dev);
234	if (vf_num == 0)
235		return -1;
236
237	/* enable VMDq and set the default pool for PF */
238	vtctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
239	vtctl |= IXGBE_VMD_CTL_VMDQ_EN;
240	vtctl &= ~IXGBE_VT_CTL_POOL_MASK;
241	vtctl |= RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx
242		<< IXGBE_VT_CTL_POOL_SHIFT;
243	vtctl |= IXGBE_VT_CTL_REPLEN;
244	IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vtctl);
245
246	vfre_offset = vf_num & VFRE_MASK;
247	vfre_slot = (vf_num >> VFRE_SHIFT) > 0 ? 1 : 0;
248
249	/* Enable pools reserved to PF only */
250	IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot), (~0U) << vfre_offset);
251	IXGBE_WRITE_REG(hw, IXGBE_VFRE(vfre_slot ^ 1), vfre_slot - 1);
252	IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot), (~0U) << vfre_offset);
253	IXGBE_WRITE_REG(hw, IXGBE_VFTE(vfre_slot ^ 1), vfre_slot - 1);
254
255	/* PFDMA Tx General Switch Control Enables VMDQ loopback */
256	IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
257
258	/* clear VMDq map to perment rar 0 */
259	hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
260
261	/* clear VMDq map to scan rar 127 */
262	IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(hw->mac.num_rar_entries), 0);
263	IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(hw->mac.num_rar_entries), 0);
264
265	/* set VMDq map to default PF pool */
266	hw->mac.ops.set_vmdq(hw, 0, RTE_ETH_DEV_SRIOV(eth_dev).def_vmdq_idx);
267
268	/*
269	 * SW msut set GCR_EXT.VT_Mode the same as GPIE.VT_Mode
270	 */
271	gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
272	gcr_ext &= ~IXGBE_GCR_EXT_VT_MODE_MASK;
273
274	gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
275	gpie &= ~IXGBE_GPIE_VTMODE_MASK;
276	gpie |= IXGBE_GPIE_MSIX_MODE;
277
278	switch (RTE_ETH_DEV_SRIOV(eth_dev).active) {
279	case ETH_64_POOLS:
280		gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
281		gpie |= IXGBE_GPIE_VTMODE_64;
282		break;
283	case ETH_32_POOLS:
284		gcr_ext |= IXGBE_GCR_EXT_VT_MODE_32;
285		gpie |= IXGBE_GPIE_VTMODE_32;
286		break;
287	case ETH_16_POOLS:
288		gcr_ext |= IXGBE_GCR_EXT_VT_MODE_16;
289		gpie |= IXGBE_GPIE_VTMODE_16;
290		break;
291	}
292
293	IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
294	IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
295
296	/*
297	 * enable vlan filtering and allow all vlan tags through
298	 */
299	vlanctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
300	vlanctrl |= IXGBE_VLNCTRL_VFE; /* enable vlan filters */
301	IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlanctrl);
302
303	/* VFTA - enable all vlan filters */
304	for (i = 0; i < IXGBE_MAX_VFTA; i++)
305		IXGBE_WRITE_REG(hw, IXGBE_VFTA(i), 0xFFFFFFFF);
306
307	/* Enable MAC Anti-Spoofing */
308	hw->mac.ops.set_mac_anti_spoofing(hw, FALSE, vf_num);
309
310	/* set flow control threshold to max to avoid tx switch hang */
311	for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
312		IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
313		fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
314		IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
315	}
316
317	ixgbe_add_tx_flow_control_drop_filter(eth_dev);
318
319	return 0;
320}
321
322static void
323set_rx_mode(struct rte_eth_dev *dev)
324{
325	struct rte_eth_dev_data *dev_data = dev->data;
326	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
327	u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
328	uint16_t vfn = dev_num_vf(dev);
329
330	/* Check for Promiscuous and All Multicast modes */
331	fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
332
333	/* set all bits that we expect to always be set */
334	fctrl &= ~IXGBE_FCTRL_SBP; /* disable store-bad-packets */
335	fctrl |= IXGBE_FCTRL_BAM;
336
337	/* clear the bits we are changing the status of */
338	fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
339
340	if (dev_data->promiscuous) {
341		fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
342		vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
343	} else {
344		if (dev_data->all_multicast) {
345			fctrl |= IXGBE_FCTRL_MPE;
346			vmolr |= IXGBE_VMOLR_MPE;
347		} else {
348			vmolr |= IXGBE_VMOLR_ROMPE;
349		}
350	}
351
352	if (hw->mac.type != ixgbe_mac_82598EB) {
353		vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(vfn)) &
354			 ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
355			   IXGBE_VMOLR_ROPE);
356		IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vfn), vmolr);
357	}
358
359	IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
360
361	if (dev->data->dev_conf.rxmode.hw_vlan_strip)
362		ixgbe_vlan_hw_strip_enable_all(dev);
363	else
364		ixgbe_vlan_hw_strip_disable_all(dev);
365}
366
367static inline void
368ixgbe_vf_reset_event(struct rte_eth_dev *dev, uint16_t vf)
369{
370	struct ixgbe_hw *hw =
371		IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
372	struct ixgbe_vf_info *vfinfo =
373		*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
374	int rar_entry = hw->mac.num_rar_entries - (vf + 1);
375	uint32_t vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
376
377	vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_ROMPE |
378			IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE);
379	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
380
381	IXGBE_WRITE_REG(hw, IXGBE_VMVIR(vf), 0);
382
383	/* reset multicast table array for vf */
384	vfinfo[vf].num_vf_mc_hashes = 0;
385
386	/* reset rx mode */
387	set_rx_mode(dev);
388
389	hw->mac.ops.clear_rar(hw, rar_entry);
390}
391
392static inline void
393ixgbe_vf_reset_msg(struct rte_eth_dev *dev, uint16_t vf)
394{
395	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
396	uint32_t reg;
397	uint32_t reg_offset, vf_shift;
398	const uint8_t VFRE_SHIFT = 5;  /* VFRE 32 bits per slot */
399	const uint8_t VFRE_MASK = (uint8_t)((1U << VFRE_SHIFT) - 1);
400
401	vf_shift = vf & VFRE_MASK;
402	reg_offset = (vf >> VFRE_SHIFT) > 0 ? 1 : 0;
403
404	/* enable transmit and receive for vf */
405	reg = IXGBE_READ_REG(hw, IXGBE_VFTE(reg_offset));
406	reg |= (reg | (1 << vf_shift));
407	IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), reg);
408
409	reg = IXGBE_READ_REG(hw, IXGBE_VFRE(reg_offset));
410	reg |= (reg | (1 << vf_shift));
411	IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), reg);
412
413	/* Enable counting of spoofed packets in the SSVPC register */
414	reg = IXGBE_READ_REG(hw, IXGBE_VMECM(reg_offset));
415	reg |= (1 << vf_shift);
416	IXGBE_WRITE_REG(hw, IXGBE_VMECM(reg_offset), reg);
417
418	ixgbe_vf_reset_event(dev, vf);
419}
420
421static int
422ixgbe_enable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
423{
424	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
425	uint32_t vmolr;
426
427	vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
428
429	RTE_LOG(INFO, PMD, "VF %u: enabling multicast promiscuous\n", vf);
430
431	vmolr |= IXGBE_VMOLR_MPE;
432
433	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
434
435	return 0;
436}
437
438static int
439ixgbe_disable_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf)
440{
441	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
442	uint32_t vmolr;
443
444	vmolr = IXGBE_READ_REG(hw, IXGBE_VMOLR(vf));
445
446	RTE_LOG(INFO, PMD, "VF %u: disabling multicast promiscuous\n", vf);
447
448	vmolr &= ~IXGBE_VMOLR_MPE;
449
450	IXGBE_WRITE_REG(hw, IXGBE_VMOLR(vf), vmolr);
451
452	return 0;
453}
454
455static int
456ixgbe_vf_reset(struct rte_eth_dev *dev, uint16_t vf, uint32_t *msgbuf)
457{
458	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
459	struct ixgbe_vf_info *vfinfo =
460		*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
461	unsigned char *vf_mac = vfinfo[vf].vf_mac_addresses;
462	int rar_entry = hw->mac.num_rar_entries - (vf + 1);
463	uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
464
465	ixgbe_vf_reset_msg(dev, vf);
466
467	hw->mac.ops.set_rar(hw, rar_entry, vf_mac, vf, IXGBE_RAH_AV);
468
469	/* Disable multicast promiscuous at reset */
470	ixgbe_disable_vf_mc_promisc(dev, vf);
471
472	/* reply to reset with ack and vf mac address */
473	msgbuf[0] = IXGBE_VF_RESET | IXGBE_VT_MSGTYPE_ACK;
474	rte_memcpy(new_mac, vf_mac, ETHER_ADDR_LEN);
475	/*
476	 * Piggyback the multicast filter type so VF can compute the
477	 * correct vectors
478	 */
479	msgbuf[3] = hw->mac.mc_filter_type;
480	ixgbe_write_mbx(hw, msgbuf, IXGBE_VF_PERMADDR_MSG_LEN, vf);
481
482	return 0;
483}
484
485static int
486ixgbe_vf_set_mac_addr(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
487{
488	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
489	struct ixgbe_vf_info *vfinfo =
490		*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
491	int rar_entry = hw->mac.num_rar_entries - (vf + 1);
492	uint8_t *new_mac = (uint8_t *)(&msgbuf[1]);
493
494	if (is_valid_assigned_ether_addr((struct ether_addr *)new_mac)) {
495		rte_memcpy(vfinfo[vf].vf_mac_addresses, new_mac, 6);
496		return hw->mac.ops.set_rar(hw, rar_entry, new_mac, vf, IXGBE_RAH_AV);
497	}
498	return -1;
499}
500
501static int
502ixgbe_vf_set_multicast(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
503{
504	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
505	struct ixgbe_vf_info *vfinfo =
506		*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
507	int nb_entries = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK) >>
508		IXGBE_VT_MSGINFO_SHIFT;
509	uint16_t *hash_list = (uint16_t *)&msgbuf[1];
510	uint32_t mta_idx;
511	uint32_t mta_shift;
512	const uint32_t IXGBE_MTA_INDEX_MASK = 0x7F;
513	const uint32_t IXGBE_MTA_BIT_SHIFT = 5;
514	const uint32_t IXGBE_MTA_BIT_MASK = (0x1 << IXGBE_MTA_BIT_SHIFT) - 1;
515	uint32_t reg_val;
516	int i;
517
518	/* Disable multicast promiscuous first */
519	ixgbe_disable_vf_mc_promisc(dev, vf);
520
521	/* only so many hash values supported */
522	nb_entries = RTE_MIN(nb_entries, IXGBE_MAX_VF_MC_ENTRIES);
523
524	/* store the mc entries  */
525	vfinfo->num_vf_mc_hashes = (uint16_t)nb_entries;
526	for (i = 0; i < nb_entries; i++) {
527		vfinfo->vf_mc_hashes[i] = hash_list[i];
528	}
529
530	for (i = 0; i < vfinfo->num_vf_mc_hashes; i++) {
531		mta_idx = (vfinfo->vf_mc_hashes[i] >> IXGBE_MTA_BIT_SHIFT)
532				& IXGBE_MTA_INDEX_MASK;
533		mta_shift = vfinfo->vf_mc_hashes[i] & IXGBE_MTA_BIT_MASK;
534		reg_val = IXGBE_READ_REG(hw, IXGBE_MTA(mta_idx));
535		reg_val |= (1 << mta_shift);
536		IXGBE_WRITE_REG(hw, IXGBE_MTA(mta_idx), reg_val);
537	}
538
539	return 0;
540}
541
542static int
543ixgbe_vf_set_vlan(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
544{
545	int add, vid;
546	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
547	struct ixgbe_vf_info *vfinfo =
548		*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
549
550	add = (msgbuf[0] & IXGBE_VT_MSGINFO_MASK)
551		>> IXGBE_VT_MSGINFO_SHIFT;
552	vid = (msgbuf[1] & IXGBE_VLVF_VLANID_MASK);
553
554	if (add)
555		vfinfo[vf].vlan_count++;
556	else if (vfinfo[vf].vlan_count)
557		vfinfo[vf].vlan_count--;
558	return hw->mac.ops.set_vfta(hw, vid, vf, (bool)add, false);
559}
560
561static int
562ixgbe_set_vf_lpe(struct rte_eth_dev *dev, __rte_unused uint32_t vf, uint32_t *msgbuf)
563{
564	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
565	uint32_t new_mtu = msgbuf[1];
566	uint32_t max_frs;
567	int max_frame = new_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN;
568
569	/* X540 and X550 support jumbo frames in IOV mode */
570	if (hw->mac.type != ixgbe_mac_X540 &&
571		hw->mac.type != ixgbe_mac_X550 &&
572		hw->mac.type != ixgbe_mac_X550EM_x &&
573		hw->mac.type != ixgbe_mac_X550EM_a)
574		return -1;
575
576	if ((max_frame < ETHER_MIN_LEN) || (max_frame > ETHER_MAX_JUMBO_FRAME_LEN))
577		return -1;
578
579	max_frs = (IXGBE_READ_REG(hw, IXGBE_MAXFRS) &
580		   IXGBE_MHADD_MFS_MASK) >> IXGBE_MHADD_MFS_SHIFT;
581	if (max_frs < new_mtu) {
582		max_frs = new_mtu << IXGBE_MHADD_MFS_SHIFT;
583		IXGBE_WRITE_REG(hw, IXGBE_MAXFRS, max_frs);
584	}
585
586	return 0;
587}
588
589static int
590ixgbe_negotiate_vf_api(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
591{
592	uint32_t api_version = msgbuf[1];
593	struct ixgbe_vf_info *vfinfo =
594		*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
595
596	switch (api_version) {
597	case ixgbe_mbox_api_10:
598	case ixgbe_mbox_api_11:
599	case ixgbe_mbox_api_12:
600		vfinfo[vf].api_version = (uint8_t)api_version;
601		return 0;
602	default:
603		break;
604	}
605
606	RTE_LOG(ERR, PMD, "Negotiate invalid api version %u from VF %d\n",
607		api_version, vf);
608
609	return -1;
610}
611
612static int
613ixgbe_get_vf_queues(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
614{
615	struct ixgbe_vf_info *vfinfo =
616		*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
617	uint32_t default_q = vf * RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
618
619	/* Verify if the PF supports the mbox APIs version or not */
620	switch (vfinfo[vf].api_version) {
621	case ixgbe_mbox_api_20:
622	case ixgbe_mbox_api_11:
623	case ixgbe_mbox_api_12:
624		break;
625	default:
626		return -1;
627	}
628
629	/* Notify VF of Rx and Tx queue number */
630	msgbuf[IXGBE_VF_RX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
631	msgbuf[IXGBE_VF_TX_QUEUES] = RTE_ETH_DEV_SRIOV(dev).nb_q_per_pool;
632
633	/* Notify VF of default queue */
634	msgbuf[IXGBE_VF_DEF_QUEUE] = default_q;
635
636	/*
637	 * FIX ME if it needs fill msgbuf[IXGBE_VF_TRANS_VLAN]
638	 * for VLAN strip or VMDQ_DCB or VMDQ_DCB_RSS
639	 */
640
641	return 0;
642}
643
644static int
645ixgbe_set_vf_mc_promisc(struct rte_eth_dev *dev, uint32_t vf, uint32_t *msgbuf)
646{
647	struct ixgbe_vf_info *vfinfo =
648		*(IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private));
649	bool enable = !!msgbuf[1];	/* msgbuf contains the flag to enable */
650
651	switch (vfinfo[vf].api_version) {
652	case ixgbe_mbox_api_12:
653		break;
654	default:
655		return -1;
656	}
657
658	if (enable)
659		return ixgbe_enable_vf_mc_promisc(dev, vf);
660	else
661		return ixgbe_disable_vf_mc_promisc(dev, vf);
662}
663
664static int
665ixgbe_rcv_msg_from_vf(struct rte_eth_dev *dev, uint16_t vf)
666{
667	uint16_t mbx_size = IXGBE_VFMAILBOX_SIZE;
668	uint16_t msg_size = IXGBE_VF_MSG_SIZE_DEFAULT;
669	uint32_t msgbuf[IXGBE_VFMAILBOX_SIZE];
670	int32_t retval;
671	struct ixgbe_hw *hw = IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
672	struct ixgbe_vf_info *vfinfo =
673		*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
674	struct rte_pmd_ixgbe_mb_event_param cb_param;
675
676	retval = ixgbe_read_mbx(hw, msgbuf, mbx_size, vf);
677	if (retval) {
678		PMD_DRV_LOG(ERR, "Error mbx recv msg from VF %d", vf);
679		return retval;
680	}
681
682	/* do nothing with the message already been processed */
683	if (msgbuf[0] & (IXGBE_VT_MSGTYPE_ACK | IXGBE_VT_MSGTYPE_NACK))
684		return retval;
685
686	/* flush the ack before we write any messages back */
687	IXGBE_WRITE_FLUSH(hw);
688
689	/**
690	 * initialise structure to send to user application
691	 * will return response from user in retval field
692	 */
693	cb_param.retval = RTE_PMD_IXGBE_MB_EVENT_PROCEED;
694	cb_param.vfid = vf;
695	cb_param.msg_type = msgbuf[0] & 0xFFFF;
696	cb_param.msg = (void *)msgbuf;
697
698	/* perform VF reset */
699	if (msgbuf[0] == IXGBE_VF_RESET) {
700		int ret = ixgbe_vf_reset(dev, vf, msgbuf);
701
702		vfinfo[vf].clear_to_send = true;
703
704		/* notify application about VF reset */
705		_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &cb_param);
706		return ret;
707	}
708
709	/**
710	 * ask user application if we allowed to perform those functions
711	 * if we get cb_param.retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED
712	 * then business as usual,
713	 * if 0, do nothing and send ACK to VF
714	 * if cb_param.retval > 1, do nothing and send NAK to VF
715	 */
716	_rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_VF_MBOX, &cb_param);
717
718	retval = cb_param.retval;
719
720	/* check & process VF to PF mailbox message */
721	switch ((msgbuf[0] & 0xFFFF)) {
722	case IXGBE_VF_SET_MAC_ADDR:
723		if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
724			retval = ixgbe_vf_set_mac_addr(dev, vf, msgbuf);
725		break;
726	case IXGBE_VF_SET_MULTICAST:
727		if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
728			retval = ixgbe_vf_set_multicast(dev, vf, msgbuf);
729		break;
730	case IXGBE_VF_SET_LPE:
731		if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
732			retval = ixgbe_set_vf_lpe(dev, vf, msgbuf);
733		break;
734	case IXGBE_VF_SET_VLAN:
735		if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
736			retval = ixgbe_vf_set_vlan(dev, vf, msgbuf);
737		break;
738	case IXGBE_VF_API_NEGOTIATE:
739		retval = ixgbe_negotiate_vf_api(dev, vf, msgbuf);
740		break;
741	case IXGBE_VF_GET_QUEUES:
742		retval = ixgbe_get_vf_queues(dev, vf, msgbuf);
743		msg_size = IXGBE_VF_GET_QUEUE_MSG_SIZE;
744		break;
745	case IXGBE_VF_UPDATE_XCAST_MODE:
746		if (retval == RTE_PMD_IXGBE_MB_EVENT_PROCEED)
747			retval = ixgbe_set_vf_mc_promisc(dev, vf, msgbuf);
748		break;
749	default:
750		PMD_DRV_LOG(DEBUG, "Unhandled Msg %8.8x", (unsigned)msgbuf[0]);
751		retval = IXGBE_ERR_MBX;
752		break;
753	}
754
755	/* response the VF according to the message process result */
756	if (retval)
757		msgbuf[0] |= IXGBE_VT_MSGTYPE_NACK;
758	else
759		msgbuf[0] |= IXGBE_VT_MSGTYPE_ACK;
760
761	msgbuf[0] |= IXGBE_VT_MSGTYPE_CTS;
762
763	ixgbe_write_mbx(hw, msgbuf, msg_size, vf);
764
765	return retval;
766}
767
768static inline void
769ixgbe_rcv_ack_from_vf(struct rte_eth_dev *dev, uint16_t vf)
770{
771	uint32_t msg = IXGBE_VT_MSGTYPE_NACK;
772	struct ixgbe_hw *hw =
773		IXGBE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
774	struct ixgbe_vf_info *vfinfo =
775		*IXGBE_DEV_PRIVATE_TO_P_VFDATA(dev->data->dev_private);
776
777	if (!vfinfo[vf].clear_to_send)
778		ixgbe_write_mbx(hw, &msg, 1, vf);
779}
780
781void ixgbe_pf_mbx_process(struct rte_eth_dev *eth_dev)
782{
783	uint16_t vf;
784	struct ixgbe_hw *hw =
785		IXGBE_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
786
787	for (vf = 0; vf < dev_num_vf(eth_dev); vf++) {
788		/* check & process vf function level reset */
789		if (!ixgbe_check_for_rst(hw, vf))
790			ixgbe_vf_reset_event(eth_dev, vf);
791
792		/* check & process vf mailbox messages */
793		if (!ixgbe_check_for_msg(hw, vf))
794			ixgbe_rcv_msg_from_vf(eth_dev, vf);
795
796		/* check & process acks from vf */
797		if (!ixgbe_check_for_ack(hw, vf))
798			ixgbe_rcv_ack_from_vf(eth_dev, vf);
799	}
800}
801