1a551c94aSIdo Barnea/*-
2a551c94aSIdo Barnea *   BSD LICENSE
3a551c94aSIdo Barnea *
4a551c94aSIdo Barnea *   Copyright (c) 2015 - 2016 CESNET
5a551c94aSIdo Barnea *   All rights reserved.
6a551c94aSIdo Barnea *
7a551c94aSIdo Barnea *   Redistribution and use in source and binary forms, with or without
8a551c94aSIdo Barnea *   modification, are permitted provided that the following conditions
9a551c94aSIdo Barnea *   are met:
10a551c94aSIdo Barnea *
11a551c94aSIdo Barnea *     * Redistributions of source code must retain the above copyright
12a551c94aSIdo Barnea *       notice, this list of conditions and the following disclaimer.
13a551c94aSIdo Barnea *     * Redistributions in binary form must reproduce the above copyright
14a551c94aSIdo Barnea *       notice, this list of conditions and the following disclaimer in
15a551c94aSIdo Barnea *       the documentation and/or other materials provided with the
16a551c94aSIdo Barnea *       distribution.
17a551c94aSIdo Barnea *     * Neither the name of CESNET nor the names of its
18a551c94aSIdo Barnea *       contributors may be used to endorse or promote products derived
19a551c94aSIdo Barnea *       from this software without specific prior written permission.
20a551c94aSIdo Barnea *
21a551c94aSIdo Barnea *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22a551c94aSIdo Barnea *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23a551c94aSIdo Barnea *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24a551c94aSIdo Barnea *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25a551c94aSIdo Barnea *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26a551c94aSIdo Barnea *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27a551c94aSIdo Barnea *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28a551c94aSIdo Barnea *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29a551c94aSIdo Barnea *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30a551c94aSIdo Barnea *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31a551c94aSIdo Barnea *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32a551c94aSIdo Barnea */
33a551c94aSIdo Barnea
34a551c94aSIdo Barnea#ifndef RTE_PMD_SZEDATA2_H_
35a551c94aSIdo Barnea#define RTE_PMD_SZEDATA2_H_
36a551c94aSIdo Barnea
37a551c94aSIdo Barnea#include <stdbool.h>
38a551c94aSIdo Barnea
39a551c94aSIdo Barnea#include <rte_byteorder.h>
40a551c94aSIdo Barnea
41a551c94aSIdo Barnea/* PCI Vendor ID */
42a551c94aSIdo Barnea#define PCI_VENDOR_ID_NETCOPE 0x1b26
43a551c94aSIdo Barnea
44a551c94aSIdo Barnea/* PCI Device IDs */
45a551c94aSIdo Barnea#define PCI_DEVICE_ID_NETCOPE_COMBO80G 0xcb80
46a551c94aSIdo Barnea#define PCI_DEVICE_ID_NETCOPE_COMBO100G 0xc1c1
47a551c94aSIdo Barnea#define PCI_DEVICE_ID_NETCOPE_COMBO100G2 0xc2c1
48a551c94aSIdo Barnea
49a551c94aSIdo Barnea/* number of PCI resource used by COMBO card */
50a551c94aSIdo Barnea#define PCI_RESOURCE_NUMBER 0
51a551c94aSIdo Barnea
52a551c94aSIdo Barnea/* szedata2_packet header length == 4 bytes == 2B segment size + 2B hw size */
53a551c94aSIdo Barnea#define RTE_SZE2_PACKET_HEADER_SIZE 4
54a551c94aSIdo Barnea
55a551c94aSIdo Barnea#define RTE_SZE2_MMIO_MAX 10
56a551c94aSIdo Barnea
57a551c94aSIdo Barnea/*!
58a551c94aSIdo Barnea * Round 'what' to the nearest larger (or equal) multiple of '8'
59a551c94aSIdo Barnea * (szedata2 packet is aligned to 8 bytes)
60a551c94aSIdo Barnea */
61a551c94aSIdo Barnea#define RTE_SZE2_ALIGN8(what) (((what) + ((8) - 1)) & (~((8) - 1)))
62a551c94aSIdo Barnea
63a551c94aSIdo Barnea/*! main handle structure */
64a551c94aSIdo Barneastruct szedata {
65a551c94aSIdo Barnea	int fd;
66a551c94aSIdo Barnea	struct sze2_instance_info *info;
67a551c94aSIdo Barnea	uint32_t *write_size;
68a551c94aSIdo Barnea	void *space[RTE_SZE2_MMIO_MAX];
69a551c94aSIdo Barnea	struct szedata_lock lock[2][2];
70a551c94aSIdo Barnea
71a551c94aSIdo Barnea	__u32 *rx_asize, *tx_asize;
72a551c94aSIdo Barnea
73a551c94aSIdo Barnea	/* szedata_read_next variables - to keep context (ct) */
74a551c94aSIdo Barnea
75a551c94aSIdo Barnea	/*
76a551c94aSIdo Barnea	 * rx
77a551c94aSIdo Barnea	 */
78a551c94aSIdo Barnea	/** initial sze lock ptr */
79a551c94aSIdo Barnea	const struct szedata_lock   *ct_rx_lck_orig;
80a551c94aSIdo Barnea	/** current sze lock ptr (initial or next) */
81a551c94aSIdo Barnea	const struct szedata_lock   *ct_rx_lck;
82a551c94aSIdo Barnea	/** remaining bytes (not read) within current lock */
83a551c94aSIdo Barnea	unsigned int                ct_rx_rem_bytes;
84a551c94aSIdo Barnea	/** current pointer to locked memory */
85a551c94aSIdo Barnea	unsigned char               *ct_rx_cur_ptr;
86a551c94aSIdo Barnea	/**
87a551c94aSIdo Barnea	 * allocated buffer to store RX packet if it was split
88a551c94aSIdo Barnea	 * into 2 buffers
89a551c94aSIdo Barnea	 */
90a551c94aSIdo Barnea	unsigned char               *ct_rx_buffer;
91a551c94aSIdo Barnea	/** registered function to provide filtering based on hwdata */
92a551c94aSIdo Barnea	int (*ct_rx_filter)(u_int16_t hwdata_len, u_char *hwdata);
93a551c94aSIdo Barnea
94a551c94aSIdo Barnea	/*
95a551c94aSIdo Barnea	 * tx
96a551c94aSIdo Barnea	 */
97a551c94aSIdo Barnea	/**
98a551c94aSIdo Barnea	 * buffer for tx - packet is prepared here
99a551c94aSIdo Barnea	 * (in future for burst write)
100a551c94aSIdo Barnea	 */
101a551c94aSIdo Barnea	unsigned char               *ct_tx_buffer;
102a551c94aSIdo Barnea	/** initial sze TX lock ptrs - number according to TX interfaces */
103a551c94aSIdo Barnea	const struct szedata_lock   **ct_tx_lck_orig;
104a551c94aSIdo Barnea	/** current sze TX lock ptrs - number according to TX interfaces */
105a551c94aSIdo Barnea	const struct szedata_lock   **ct_tx_lck;
106a551c94aSIdo Barnea	/** already written bytes in both locks */
107a551c94aSIdo Barnea	unsigned int                *ct_tx_written_bytes;
108a551c94aSIdo Barnea	/** remaining bytes (not written) within current lock */
109a551c94aSIdo Barnea	unsigned int                *ct_tx_rem_bytes;
110a551c94aSIdo Barnea	/** current pointers to locked memory */
111a551c94aSIdo Barnea	unsigned char               **ct_tx_cur_ptr;
112a551c94aSIdo Barnea	/** NUMA node closest to PCIe device, or -1 */
113a551c94aSIdo Barnea	int                         numa_node;
114a551c94aSIdo Barnea};
115a551c94aSIdo Barnea
116a551c94aSIdo Barnea/*
117a551c94aSIdo Barnea * @return Byte from PCI resource at offset "offset".
118a551c94aSIdo Barnea */
119a551c94aSIdo Barneastatic inline uint8_t
1209ca4a157SIdo Barneapci_resource_read8(struct rte_mem_resource *rsc, uint32_t offset)
121a551c94aSIdo Barnea{
1229ca4a157SIdo Barnea	return *((uint8_t *)((uint8_t *)rsc->addr + offset));
123a551c94aSIdo Barnea}
124a551c94aSIdo Barnea
125a551c94aSIdo Barnea/*
126a551c94aSIdo Barnea * @return Two bytes from PCI resource starting at offset "offset".
127a551c94aSIdo Barnea */
128a551c94aSIdo Barneastatic inline uint16_t
1299ca4a157SIdo Barneapci_resource_read16(struct rte_mem_resource *rsc, uint32_t offset)
130a551c94aSIdo Barnea{
1319ca4a157SIdo Barnea	return rte_le_to_cpu_16(*((uint16_t *)((uint8_t *)rsc->addr +
1329ca4a157SIdo Barnea					       offset)));
133a551c94aSIdo Barnea}
134a551c94aSIdo Barnea
135a551c94aSIdo Barnea/*
136a551c94aSIdo Barnea * @return Four bytes from PCI resource starting at offset "offset".
137a551c94aSIdo Barnea */
138a551c94aSIdo Barneastatic inline uint32_t
1399ca4a157SIdo Barneapci_resource_read32(struct rte_mem_resource *rsc, uint32_t offset)
140a551c94aSIdo Barnea{
1419ca4a157SIdo Barnea	return rte_le_to_cpu_32(*((uint32_t *)((uint8_t *)rsc->addr +
1429ca4a157SIdo Barnea					       offset)));
143a551c94aSIdo Barnea}
144a551c94aSIdo Barnea
145a551c94aSIdo Barnea/*
146a551c94aSIdo Barnea * @return Eight bytes from PCI resource starting at offset "offset".
147a551c94aSIdo Barnea */
148a551c94aSIdo Barneastatic inline uint64_t
1499ca4a157SIdo Barneapci_resource_read64(struct rte_mem_resource *rsc, uint32_t offset)
150a551c94aSIdo Barnea{
1519ca4a157SIdo Barnea	return rte_le_to_cpu_64(*((uint64_t *)((uint8_t *)rsc->addr +
1529ca4a157SIdo Barnea					       offset)));
153a551c94aSIdo Barnea}
154a551c94aSIdo Barnea
155a551c94aSIdo Barnea/*
156a551c94aSIdo Barnea * Write one byte to PCI resource address space at offset "offset".
157a551c94aSIdo Barnea */
158a551c94aSIdo Barneastatic inline void
1599ca4a157SIdo Barneapci_resource_write8(struct rte_mem_resource *rsc, uint32_t offset, uint8_t val)
160a551c94aSIdo Barnea{
1619ca4a157SIdo Barnea	*((uint8_t *)((uint8_t *)rsc->addr + offset)) = val;
162a551c94aSIdo Barnea}
163a551c94aSIdo Barnea
164a551c94aSIdo Barnea/*
165a551c94aSIdo Barnea * Write two bytes to PCI resource address space at offset "offset".
166a551c94aSIdo Barnea */
167a551c94aSIdo Barneastatic inline void
1689ca4a157SIdo Barneapci_resource_write16(struct rte_mem_resource *rsc, uint32_t offset,
1699ca4a157SIdo Barnea		     uint16_t val)
170a551c94aSIdo Barnea{
1719ca4a157SIdo Barnea	*((uint16_t *)((uint8_t *)rsc->addr + offset)) = rte_cpu_to_le_16(val);
172a551c94aSIdo Barnea}
173a551c94aSIdo Barnea
174a551c94aSIdo Barnea/*
175a551c94aSIdo Barnea * Write four bytes to PCI resource address space at offset "offset".
176a551c94aSIdo Barnea */
177a551c94aSIdo Barneastatic inline void
1789ca4a157SIdo Barneapci_resource_write32(struct rte_mem_resource *rsc, uint32_t offset,
1799ca4a157SIdo Barnea		     uint32_t val)
180a551c94aSIdo Barnea{
1819ca4a157SIdo Barnea	*((uint32_t *)((uint8_t *)rsc->addr + offset)) = rte_cpu_to_le_32(val);
182a551c94aSIdo Barnea}
183a551c94aSIdo Barnea
184a551c94aSIdo Barnea/*
185a551c94aSIdo Barnea * Write eight bytes to PCI resource address space at offset "offset".
186a551c94aSIdo Barnea */
187a551c94aSIdo Barneastatic inline void
1889ca4a157SIdo Barneapci_resource_write64(struct rte_mem_resource *rsc, uint32_t offset,
1899ca4a157SIdo Barnea		     uint64_t val)
190a551c94aSIdo Barnea{
1919ca4a157SIdo Barnea	*((uint64_t *)((uint8_t *)rsc->addr + offset)) = rte_cpu_to_le_64(val);
192a551c94aSIdo Barnea}
193a551c94aSIdo Barnea
1949ca4a157SIdo Barnea#define SZEDATA2_PCI_RESOURCE_PTR(rsc, offset, type) \
1959ca4a157SIdo Barnea	((type)(((uint8_t *)(rsc)->addr) + (offset)))
196a551c94aSIdo Barnea
197a551c94aSIdo Barneaenum szedata2_link_speed {
198a551c94aSIdo Barnea	SZEDATA2_LINK_SPEED_DEFAULT = 0,
199a551c94aSIdo Barnea	SZEDATA2_LINK_SPEED_10G,
200a551c94aSIdo Barnea	SZEDATA2_LINK_SPEED_40G,
201a551c94aSIdo Barnea	SZEDATA2_LINK_SPEED_100G,
202a551c94aSIdo Barnea};
203a551c94aSIdo Barnea
204a551c94aSIdo Barneaenum szedata2_mac_check_mode {
205a551c94aSIdo Barnea	SZEDATA2_MAC_CHMODE_PROMISC       = 0x0,
206a551c94aSIdo Barnea	SZEDATA2_MAC_CHMODE_ONLY_VALID    = 0x1,
207a551c94aSIdo Barnea	SZEDATA2_MAC_CHMODE_ALL_BROADCAST = 0x2,
208a551c94aSIdo Barnea	SZEDATA2_MAC_CHMODE_ALL_MULTICAST = 0x3,
209a551c94aSIdo Barnea};
210a551c94aSIdo Barnea
211a551c94aSIdo Barnea/*
212a551c94aSIdo Barnea * Structure describes CGMII IBUF address space
213a551c94aSIdo Barnea */
214a551c94aSIdo Barneastruct szedata2_cgmii_ibuf {
215a551c94aSIdo Barnea	/** Total Received Frames Counter low part */
216a551c94aSIdo Barnea	uint32_t trfcl;
217a551c94aSIdo Barnea	/** Correct Frames Counter low part */
218a551c94aSIdo Barnea	uint32_t cfcl;
219a551c94aSIdo Barnea	/** Discarded Frames Counter low part */
220a551c94aSIdo Barnea	uint32_t dfcl;
221a551c94aSIdo Barnea	/** Counter of frames discarded due to buffer overflow low part */
222a551c94aSIdo Barnea	uint32_t bodfcl;
223a551c94aSIdo Barnea	/** Total Received Frames Counter high part */
224a551c94aSIdo Barnea	uint32_t trfch;
225a551c94aSIdo Barnea	/** Correct Frames Counter high part */
226a551c94aSIdo Barnea	uint32_t cfch;
227a551c94aSIdo Barnea	/** Discarded Frames Counter high part */
228a551c94aSIdo Barnea	uint32_t dfch;
229a551c94aSIdo Barnea	/** Counter of frames discarded due to buffer overflow high part */
230a551c94aSIdo Barnea	uint32_t bodfch;
231a551c94aSIdo Barnea	/** IBUF enable register */
232a551c94aSIdo Barnea	uint32_t ibuf_en;
233a551c94aSIdo Barnea	/** Error mask register */
234a551c94aSIdo Barnea	uint32_t err_mask;
235a551c94aSIdo Barnea	/** IBUF status register */
236a551c94aSIdo Barnea	uint32_t ibuf_st;
237a551c94aSIdo Barnea	/** IBUF command register */
238a551c94aSIdo Barnea	uint32_t ibuf_cmd;
239a551c94aSIdo Barnea	/** Minimum frame length allowed */
240a551c94aSIdo Barnea	uint32_t mfla;
241a551c94aSIdo Barnea	/** Frame MTU */
242a551c94aSIdo Barnea	uint32_t mtu;
243a551c94aSIdo Barnea	/** MAC address check mode */
244a551c94aSIdo Barnea	uint32_t mac_chmode;
245a551c94aSIdo Barnea	/** Octets Received OK Counter low part */
246a551c94aSIdo Barnea	uint32_t orocl;
247a551c94aSIdo Barnea	/** Octets Received OK Counter high part */
248a551c94aSIdo Barnea	uint32_t oroch;
249a551c94aSIdo Barnea} __rte_packed;
250a551c94aSIdo Barnea
251a551c94aSIdo Barnea/* Offset of CGMII IBUF memory for MAC addresses */
252a551c94aSIdo Barnea#define SZEDATA2_CGMII_IBUF_MAC_MEM_OFF 0x80
253a551c94aSIdo Barnea
254a551c94aSIdo Barnea/*
255a551c94aSIdo Barnea * @return
256a551c94aSIdo Barnea *     true if IBUF is enabled
257a551c94aSIdo Barnea *     false if IBUF is disabled
258a551c94aSIdo Barnea */
259a551c94aSIdo Barneastatic inline bool
260a551c94aSIdo Barneacgmii_ibuf_is_enabled(volatile struct szedata2_cgmii_ibuf *ibuf)
261a551c94aSIdo Barnea{
262a551c94aSIdo Barnea	return ((rte_le_to_cpu_32(ibuf->ibuf_en) & 0x1) != 0) ? true : false;
263a551c94aSIdo Barnea}
264a551c94aSIdo Barnea
265a551c94aSIdo Barnea/*
266a551c94aSIdo Barnea * Enables IBUF.
267a551c94aSIdo Barnea */
268a551c94aSIdo Barneastatic inline void
269a551c94aSIdo Barneacgmii_ibuf_enable(volatile struct szedata2_cgmii_ibuf *ibuf)
270a551c94aSIdo Barnea{
271a551c94aSIdo Barnea	ibuf->ibuf_en =
272a551c94aSIdo Barnea		rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) | 0x1);
273a551c94aSIdo Barnea}
274a551c94aSIdo Barnea
275a551c94aSIdo Barnea/*
276a551c94aSIdo Barnea * Disables IBUF.
277a551c94aSIdo Barnea */
278a551c94aSIdo Barneastatic inline void
279a551c94aSIdo Barneacgmii_ibuf_disable(volatile struct szedata2_cgmii_ibuf *ibuf)
280a551c94aSIdo Barnea{
281a551c94aSIdo Barnea	ibuf->ibuf_en =
282a551c94aSIdo Barnea		rte_cpu_to_le_32(rte_le_to_cpu_32(ibuf->ibuf_en) & ~0x1);
283a551c94aSIdo Barnea}
284a551c94aSIdo Barnea
285a551c94aSIdo Barnea/*
286a551c94aSIdo Barnea * @return
287a551c94aSIdo Barnea *     true if ibuf link is up
288a551c94aSIdo Barnea *     false if ibuf link is down
289a551c94aSIdo Barnea */
290a551c94aSIdo Barneastatic inline bool
291a551c94aSIdo Barneacgmii_ibuf_is_link_up(volatile struct szedata2_cgmii_ibuf *ibuf)
292a551c94aSIdo Barnea{
293a551c94aSIdo Barnea	return ((rte_le_to_cpu_32(ibuf->ibuf_st) & 0x80) != 0) ? true : false;
294a551c94aSIdo Barnea}
295a551c94aSIdo Barnea
296a551c94aSIdo Barnea/*
297a551c94aSIdo Barnea * @return
298a551c94aSIdo Barnea *     MAC address check mode
299a551c94aSIdo Barnea */
300a551c94aSIdo Barneastatic inline enum szedata2_mac_check_mode
301a551c94aSIdo Barneacgmii_ibuf_mac_mode_read(volatile struct szedata2_cgmii_ibuf *ibuf)
302a551c94aSIdo Barnea{
303a551c94aSIdo Barnea	switch (rte_le_to_cpu_32(ibuf->mac_chmode) & 0x3) {
304a551c94aSIdo Barnea	case 0x0:
305a551c94aSIdo Barnea		return SZEDATA2_MAC_CHMODE_PROMISC;
306a551c94aSIdo Barnea	case 0x1:
307a551c94aSIdo Barnea		return SZEDATA2_MAC_CHMODE_ONLY_VALID;
308a551c94aSIdo Barnea	case 0x2:
309a551c94aSIdo Barnea		return SZEDATA2_MAC_CHMODE_ALL_BROADCAST;
310a551c94aSIdo Barnea	case 0x3:
311a551c94aSIdo Barnea		return SZEDATA2_MAC_CHMODE_ALL_MULTICAST;
312a551c94aSIdo Barnea	default:
313a551c94aSIdo Barnea		return SZEDATA2_MAC_CHMODE_PROMISC;
314a551c94aSIdo Barnea	}
315a551c94aSIdo Barnea}
316a551c94aSIdo Barnea
317a551c94aSIdo Barnea/*
318a551c94aSIdo Barnea * Writes "mode" in MAC address check mode register.
319a551c94aSIdo Barnea */
320a551c94aSIdo Barneastatic inline void
321a551c94aSIdo Barneacgmii_ibuf_mac_mode_write(volatile struct szedata2_cgmii_ibuf *ibuf,
322a551c94aSIdo Barnea		enum szedata2_mac_check_mode mode)
323a551c94aSIdo Barnea{
324a551c94aSIdo Barnea	ibuf->mac_chmode = rte_cpu_to_le_32(
325a551c94aSIdo Barnea			(rte_le_to_cpu_32(ibuf->mac_chmode) & ~0x3) | mode);
326a551c94aSIdo Barnea}
327a551c94aSIdo Barnea
328a551c94aSIdo Barnea/*
329a551c94aSIdo Barnea * Structure describes CGMII OBUF address space
330a551c94aSIdo Barnea */
331a551c94aSIdo Barneastruct szedata2_cgmii_obuf {
332a551c94aSIdo Barnea	/** Total Sent Frames Counter low part */
333a551c94aSIdo Barnea	uint32_t tsfcl;
334a551c94aSIdo Barnea	/** Octets Sent Counter low part */
335a551c94aSIdo Barnea	uint32_t oscl;
336a551c94aSIdo Barnea	/** Total Discarded Frames Counter low part */
337a551c94aSIdo Barnea	uint32_t tdfcl;
338a551c94aSIdo Barnea	/** reserved */
339a551c94aSIdo Barnea	uint32_t reserved1;
340a551c94aSIdo Barnea	/** Total Sent Frames Counter high part */
341a551c94aSIdo Barnea	uint32_t tsfch;
342a551c94aSIdo Barnea	/** Octets Sent Counter high part */
343a551c94aSIdo Barnea	uint32_t osch;
344a551c94aSIdo Barnea	/** Total Discarded Frames Counter high part */
345a551c94aSIdo Barnea	uint32_t tdfch;
346a551c94aSIdo Barnea	/** reserved */
347a551c94aSIdo Barnea	uint32_t reserved2;
348a551c94aSIdo Barnea	/** OBUF enable register */
349a551c94aSIdo Barnea	uint32_t obuf_en;
350a551c94aSIdo Barnea	/** reserved */
351a551c94aSIdo Barnea	uint64_t reserved3;
352a551c94aSIdo Barnea	/** OBUF control register */
353a551c94aSIdo Barnea	uint32_t ctrl;
354a551c94aSIdo Barnea	/** OBUF status register */
355a551c94aSIdo Barnea	uint32_t obuf_st;
356a551c94aSIdo Barnea} __rte_packed;
357a551c94aSIdo Barnea
358a551c94aSIdo Barnea/*
359a551c94aSIdo Barnea * @return
360a551c94aSIdo Barnea *     true if OBUF is enabled
361a551c94aSIdo Barnea *     false if OBUF is disabled
362a551c94aSIdo Barnea */
363a551c94aSIdo Barneastatic inline bool
364a551c94aSIdo Barneacgmii_obuf_is_enabled(volatile struct szedata2_cgmii_obuf *obuf)
365a551c94aSIdo Barnea{
366a551c94aSIdo Barnea	return ((rte_le_to_cpu_32(obuf->obuf_en) & 0x1) != 0) ? true : false;
367a551c94aSIdo Barnea}
368a551c94aSIdo Barnea
369a551c94aSIdo Barnea/*
370a551c94aSIdo Barnea * Enables OBUF.
371a551c94aSIdo Barnea */
372a551c94aSIdo Barneastatic inline void
373a551c94aSIdo Barneacgmii_obuf_enable(volatile struct szedata2_cgmii_obuf *obuf)
374a551c94aSIdo Barnea{
375a551c94aSIdo Barnea	obuf->obuf_en =
376a551c94aSIdo Barnea		rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) | 0x1);
377a551c94aSIdo Barnea}
378a551c94aSIdo Barnea
379a551c94aSIdo Barnea/*
380a551c94aSIdo Barnea * Disables OBUF.
381a551c94aSIdo Barnea */
382a551c94aSIdo Barneastatic inline void
383a551c94aSIdo Barneacgmii_obuf_disable(volatile struct szedata2_cgmii_obuf *obuf)
384a551c94aSIdo Barnea{
385a551c94aSIdo Barnea	obuf->obuf_en =
386a551c94aSIdo Barnea		rte_cpu_to_le_32(rte_le_to_cpu_32(obuf->obuf_en) & ~0x1);
387a551c94aSIdo Barnea}
388a551c94aSIdo Barnea
389a551c94aSIdo Barnea/*
390a551c94aSIdo Barnea * Function takes value from IBUF status register. Values in IBUF and OBUF
391a551c94aSIdo Barnea * should be same.
392a551c94aSIdo Barnea *
393a551c94aSIdo Barnea * @return Link speed constant.
394a551c94aSIdo Barnea */
395a551c94aSIdo Barneastatic inline enum szedata2_link_speed
396a551c94aSIdo Barneacgmii_link_speed(volatile struct szedata2_cgmii_ibuf *ibuf)
397a551c94aSIdo Barnea{
398a551c94aSIdo Barnea	uint32_t speed = (rte_le_to_cpu_32(ibuf->ibuf_st) & 0x70) >> 4;
399a551c94aSIdo Barnea	switch (speed) {
400a551c94aSIdo Barnea	case 0x03:
401a551c94aSIdo Barnea		return SZEDATA2_LINK_SPEED_10G;
402a551c94aSIdo Barnea	case 0x04:
403a551c94aSIdo Barnea		return SZEDATA2_LINK_SPEED_40G;
404a551c94aSIdo Barnea	case 0x05:
405a551c94aSIdo Barnea		return SZEDATA2_LINK_SPEED_100G;
406a551c94aSIdo Barnea	default:
407a551c94aSIdo Barnea		return SZEDATA2_LINK_SPEED_DEFAULT;
408a551c94aSIdo Barnea	}
409a551c94aSIdo Barnea}
410a551c94aSIdo Barnea
411a551c94aSIdo Barnea/*
412a551c94aSIdo Barnea * IBUFs and OBUFs can generally be located at different offsets in different
413a551c94aSIdo Barnea * firmwares.
414a551c94aSIdo Barnea * This part defines base offsets of IBUFs and OBUFs through various firmwares.
415a551c94aSIdo Barnea * Currently one firmware type is supported.
416a551c94aSIdo Barnea * Type of firmware is set through configuration option
417a551c94aSIdo Barnea * CONFIG_RTE_LIBRTE_PMD_SZEDATA_AS.
418a551c94aSIdo Barnea * Possible values are:
419a551c94aSIdo Barnea * 0 - for firmwares:
420a551c94aSIdo Barnea *     NIC_100G1_LR4
421a551c94aSIdo Barnea *     HANIC_100G1_LR4
422a551c94aSIdo Barnea *     HANIC_100G1_SR10
423a551c94aSIdo Barnea */
424a551c94aSIdo Barnea#if !defined(RTE_LIBRTE_PMD_SZEDATA2_AS)
425a551c94aSIdo Barnea#error "RTE_LIBRTE_PMD_SZEDATA2_AS has to be defined"
426a551c94aSIdo Barnea#elif RTE_LIBRTE_PMD_SZEDATA2_AS == 0
427a551c94aSIdo Barnea
428a551c94aSIdo Barnea/*
429a551c94aSIdo Barnea * CGMII IBUF offset from the beginning of PCI resource address space.
430a551c94aSIdo Barnea */
431a551c94aSIdo Barnea#define SZEDATA2_CGMII_IBUF_BASE_OFF 0x8000
432a551c94aSIdo Barnea/*
433a551c94aSIdo Barnea * Size of CGMII IBUF.
434a551c94aSIdo Barnea */
435a551c94aSIdo Barnea#define SZEDATA2_CGMII_IBUF_SIZE 0x200
436a551c94aSIdo Barnea
437a551c94aSIdo Barnea/*
438a551c94aSIdo Barnea * GCMII OBUF offset from the beginning of PCI resource address space.
439a551c94aSIdo Barnea */
440a551c94aSIdo Barnea#define SZEDATA2_CGMII_OBUF_BASE_OFF 0x9000
441a551c94aSIdo Barnea/*
442a551c94aSIdo Barnea * Size of CGMII OBUF.
443a551c94aSIdo Barnea */
444a551c94aSIdo Barnea#define SZEDATA2_CGMII_OBUF_SIZE 0x100
445a551c94aSIdo Barnea
446a551c94aSIdo Barnea#else
447a551c94aSIdo Barnea#error "RTE_LIBRTE_PMD_SZEDATA2_AS has wrong value, see comments in config file"
448a551c94aSIdo Barnea#endif
449a551c94aSIdo Barnea
450a551c94aSIdo Barnea#endif
451