1/*-
2 * GPL LICENSE SUMMARY
3 *
4 *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
5 *
6 *   This program is free software; you can redistribute it and/or modify
7 *   it under the terms of version 2 of the GNU General Public License as
8 *   published by the Free Software Foundation.
9 *
10 *   This program is distributed in the hope that it will be useful, but
11 *   WITHOUT ANY WARRANTY; without even the implied warranty of
12 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
13 *   General Public License for more details.
14 *
15 *   You should have received a copy of the GNU General Public License
16 *   along with this program; if not, write to the Free Software
17 *   Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 *   The full GNU General Public License is included in this distribution
19 *   in the file called LICENSE.GPL.
20 *
21 *   Contact Information:
22 *   Intel Corporation
23 */
24
25#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
26
27#include <linux/device.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/uio_driver.h>
31#include <linux/io.h>
32#include <linux/msi.h>
33#include <linux/version.h>
34#include <linux/slab.h>
35
36#ifdef CONFIG_XEN_DOM0
37#include <xen/xen.h>
38#endif
39#include <rte_pci_dev_features.h>
40
41#include "compat.h"
42
43/**
44 * A structure describing the private information for a uio device.
45 */
46struct rte_uio_pci_dev {
47	struct uio_info info;
48	struct pci_dev *pdev;
49	enum rte_intr_mode mode;
50};
51
52static char *intr_mode;
53static enum rte_intr_mode igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
54
55/* sriov sysfs */
56static ssize_t
57show_max_vfs(struct device *dev, struct device_attribute *attr,
58	     char *buf)
59{
60	return snprintf(buf, 10, "%u\n", dev_num_vf(dev));
61}
62
63static ssize_t
64store_max_vfs(struct device *dev, struct device_attribute *attr,
65	      const char *buf, size_t count)
66{
67	int err = 0;
68	unsigned long max_vfs;
69	struct pci_dev *pdev = to_pci_dev(dev);
70
71	if (0 != kstrtoul(buf, 0, &max_vfs))
72		return -EINVAL;
73
74	if (0 == max_vfs)
75		pci_disable_sriov(pdev);
76	else if (0 == pci_num_vf(pdev))
77		err = pci_enable_sriov(pdev, max_vfs);
78	else /* do nothing if change max_vfs number */
79		err = -EINVAL;
80
81	return err ? err : count;
82}
83
84static DEVICE_ATTR(max_vfs, S_IRUGO | S_IWUSR, show_max_vfs, store_max_vfs);
85
86static struct attribute *dev_attrs[] = {
87	&dev_attr_max_vfs.attr,
88	NULL,
89};
90
91static const struct attribute_group dev_attr_grp = {
92	.attrs = dev_attrs,
93};
94/*
95 * It masks the msix on/off of generating MSI-X messages.
96 */
97static void
98igbuio_msix_mask_irq(struct msi_desc *desc, int32_t state)
99{
100	u32 mask_bits = desc->masked;
101	unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
102						PCI_MSIX_ENTRY_VECTOR_CTRL;
103
104	if (state != 0)
105		mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
106	else
107		mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
108
109	if (mask_bits != desc->masked) {
110		writel(mask_bits, desc->mask_base + offset);
111		readl(desc->mask_base);
112		desc->masked = mask_bits;
113	}
114}
115
116/**
117 * This is the irqcontrol callback to be registered to uio_info.
118 * It can be used to disable/enable interrupt from user space processes.
119 *
120 * @param info
121 *  pointer to uio_info.
122 * @param irq_state
123 *  state value. 1 to enable interrupt, 0 to disable interrupt.
124 *
125 * @return
126 *  - On success, 0.
127 *  - On failure, a negative value.
128 */
129static int
130igbuio_pci_irqcontrol(struct uio_info *info, s32 irq_state)
131{
132	struct rte_uio_pci_dev *udev = info->priv;
133	struct pci_dev *pdev = udev->pdev;
134
135	pci_cfg_access_lock(pdev);
136	if (udev->mode == RTE_INTR_MODE_LEGACY)
137		pci_intx(pdev, !!irq_state);
138
139	else if (udev->mode == RTE_INTR_MODE_MSIX) {
140		struct msi_desc *desc;
141
142#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 3, 0))
143		list_for_each_entry(desc, &pdev->msi_list, list)
144			igbuio_msix_mask_irq(desc, irq_state);
145#else
146		list_for_each_entry(desc, &pdev->dev.msi_list, list)
147			igbuio_msix_mask_irq(desc, irq_state);
148#endif
149	}
150	pci_cfg_access_unlock(pdev);
151
152	return 0;
153}
154
155/**
156 * This is interrupt handler which will check if the interrupt is for the right device.
157 * If yes, disable it here and will be enable later.
158 */
159static irqreturn_t
160igbuio_pci_irqhandler(int irq, struct uio_info *info)
161{
162	struct rte_uio_pci_dev *udev = info->priv;
163
164	/* Legacy mode need to mask in hardware */
165	if (udev->mode == RTE_INTR_MODE_LEGACY &&
166	    !pci_check_and_mask_intx(udev->pdev))
167		return IRQ_NONE;
168
169	/* Message signal mode, no share IRQ and automasked */
170	return IRQ_HANDLED;
171}
172
173#ifdef CONFIG_XEN_DOM0
174static int
175igbuio_dom0_mmap_phys(struct uio_info *info, struct vm_area_struct *vma)
176{
177	int idx;
178
179	idx = (int)vma->vm_pgoff;
180	vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
181#ifdef HAVE_PTE_MASK_PAGE_IOMAP
182	vma->vm_page_prot.pgprot |= _PAGE_IOMAP;
183#endif
184
185	return remap_pfn_range(vma,
186			vma->vm_start,
187			info->mem[idx].addr >> PAGE_SHIFT,
188			vma->vm_end - vma->vm_start,
189			vma->vm_page_prot);
190}
191
192/**
193 * This is uio device mmap method which will use igbuio mmap for Xen
194 * Dom0 environment.
195 */
196static int
197igbuio_dom0_pci_mmap(struct uio_info *info, struct vm_area_struct *vma)
198{
199	int idx;
200
201	if (vma->vm_pgoff >= MAX_UIO_MAPS)
202		return -EINVAL;
203
204	if (info->mem[vma->vm_pgoff].size == 0)
205		return -EINVAL;
206
207	idx = (int)vma->vm_pgoff;
208	switch (info->mem[idx].memtype) {
209	case UIO_MEM_PHYS:
210		return igbuio_dom0_mmap_phys(info, vma);
211	case UIO_MEM_LOGICAL:
212	case UIO_MEM_VIRTUAL:
213	default:
214		return -EINVAL;
215	}
216}
217#endif
218
219/* Remap pci resources described by bar #pci_bar in uio resource n. */
220static int
221igbuio_pci_setup_iomem(struct pci_dev *dev, struct uio_info *info,
222		       int n, int pci_bar, const char *name)
223{
224	unsigned long addr, len;
225	void *internal_addr;
226
227	if (n >= ARRAY_SIZE(info->mem))
228		return -EINVAL;
229
230	addr = pci_resource_start(dev, pci_bar);
231	len = pci_resource_len(dev, pci_bar);
232	if (addr == 0 || len == 0)
233		return -1;
234	internal_addr = ioremap(addr, len);
235	if (internal_addr == NULL)
236		return -1;
237	info->mem[n].name = name;
238	info->mem[n].addr = addr;
239	info->mem[n].internal_addr = internal_addr;
240	info->mem[n].size = len;
241	info->mem[n].memtype = UIO_MEM_PHYS;
242	return 0;
243}
244
245/* Get pci port io resources described by bar #pci_bar in uio resource n. */
246static int
247igbuio_pci_setup_ioport(struct pci_dev *dev, struct uio_info *info,
248		int n, int pci_bar, const char *name)
249{
250	unsigned long addr, len;
251
252	if (n >= ARRAY_SIZE(info->port))
253		return -EINVAL;
254
255	addr = pci_resource_start(dev, pci_bar);
256	len = pci_resource_len(dev, pci_bar);
257	if (addr == 0 || len == 0)
258		return -EINVAL;
259
260	info->port[n].name = name;
261	info->port[n].start = addr;
262	info->port[n].size = len;
263	info->port[n].porttype = UIO_PORT_X86;
264
265	return 0;
266}
267
268/* Unmap previously ioremap'd resources */
269static void
270igbuio_pci_release_iomem(struct uio_info *info)
271{
272	int i;
273
274	for (i = 0; i < MAX_UIO_MAPS; i++) {
275		if (info->mem[i].internal_addr)
276			iounmap(info->mem[i].internal_addr);
277	}
278}
279
280static int
281igbuio_setup_bars(struct pci_dev *dev, struct uio_info *info)
282{
283	int i, iom, iop, ret;
284	unsigned long flags;
285	static const char *bar_names[PCI_STD_RESOURCE_END + 1]  = {
286		"BAR0",
287		"BAR1",
288		"BAR2",
289		"BAR3",
290		"BAR4",
291		"BAR5",
292	};
293
294	iom = 0;
295	iop = 0;
296
297	for (i = 0; i < ARRAY_SIZE(bar_names); i++) {
298		if (pci_resource_len(dev, i) != 0 &&
299				pci_resource_start(dev, i) != 0) {
300			flags = pci_resource_flags(dev, i);
301			if (flags & IORESOURCE_MEM) {
302				ret = igbuio_pci_setup_iomem(dev, info, iom,
303							     i, bar_names[i]);
304				if (ret != 0)
305					return ret;
306				iom++;
307			} else if (flags & IORESOURCE_IO) {
308				ret = igbuio_pci_setup_ioport(dev, info, iop,
309							      i, bar_names[i]);
310				if (ret != 0)
311					return ret;
312				iop++;
313			}
314		}
315	}
316
317	return (iom != 0) ? ret : -ENOENT;
318}
319
320#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 8, 0)
321static int __devinit
322#else
323static int
324#endif
325igbuio_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
326{
327	struct rte_uio_pci_dev *udev;
328	struct msix_entry msix_entry;
329	int err;
330
331	udev = kzalloc(sizeof(struct rte_uio_pci_dev), GFP_KERNEL);
332	if (!udev)
333		return -ENOMEM;
334
335	/*
336	 * enable device: ask low-level code to enable I/O and
337	 * memory
338	 */
339	err = pci_enable_device(dev);
340	if (err != 0) {
341		dev_err(&dev->dev, "Cannot enable PCI device\n");
342		goto fail_free;
343	}
344
345	/* enable bus mastering on the device */
346	pci_set_master(dev);
347
348	/* remap IO memory */
349	err = igbuio_setup_bars(dev, &udev->info);
350	if (err != 0)
351		goto fail_release_iomem;
352
353	/* set 64-bit DMA mask */
354	err = pci_set_dma_mask(dev,  DMA_BIT_MASK(64));
355	if (err != 0) {
356		dev_err(&dev->dev, "Cannot set DMA mask\n");
357		goto fail_release_iomem;
358	}
359
360	err = pci_set_consistent_dma_mask(dev, DMA_BIT_MASK(64));
361	if (err != 0) {
362		dev_err(&dev->dev, "Cannot set consistent DMA mask\n");
363		goto fail_release_iomem;
364	}
365
366	/* fill uio infos */
367	udev->info.name = "igb_uio";
368	udev->info.version = "0.1";
369	udev->info.handler = igbuio_pci_irqhandler;
370	udev->info.irqcontrol = igbuio_pci_irqcontrol;
371#ifdef CONFIG_XEN_DOM0
372	/* check if the driver run on Xen Dom0 */
373	if (xen_initial_domain())
374		udev->info.mmap = igbuio_dom0_pci_mmap;
375#endif
376	udev->info.priv = udev;
377	udev->pdev = dev;
378
379	switch (igbuio_intr_mode_preferred) {
380	case RTE_INTR_MODE_MSIX:
381		/* Only 1 msi-x vector needed */
382		msix_entry.entry = 0;
383		if (pci_enable_msix(dev, &msix_entry, 1) == 0) {
384			dev_dbg(&dev->dev, "using MSI-X");
385			udev->info.irq = msix_entry.vector;
386			udev->mode = RTE_INTR_MODE_MSIX;
387			break;
388		}
389		/* fall back to INTX */
390	case RTE_INTR_MODE_LEGACY:
391		if (pci_intx_mask_supported(dev)) {
392			dev_dbg(&dev->dev, "using INTX");
393			udev->info.irq_flags = IRQF_SHARED;
394			udev->info.irq = dev->irq;
395			udev->mode = RTE_INTR_MODE_LEGACY;
396			break;
397		}
398		dev_notice(&dev->dev, "PCI INTX mask not supported\n");
399		/* fall back to no IRQ */
400	case RTE_INTR_MODE_NONE:
401		udev->mode = RTE_INTR_MODE_NONE;
402		udev->info.irq = 0;
403		break;
404
405	default:
406		dev_err(&dev->dev, "invalid IRQ mode %u",
407			igbuio_intr_mode_preferred);
408		err = -EINVAL;
409		goto fail_release_iomem;
410	}
411
412	err = sysfs_create_group(&dev->dev.kobj, &dev_attr_grp);
413	if (err != 0)
414		goto fail_release_iomem;
415
416	/* register uio driver */
417	err = uio_register_device(&dev->dev, &udev->info);
418	if (err != 0)
419		goto fail_remove_group;
420
421	pci_set_drvdata(dev, udev);
422
423	dev_info(&dev->dev, "uio device registered with irq %lx\n",
424		 udev->info.irq);
425
426	return 0;
427
428fail_remove_group:
429	sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
430fail_release_iomem:
431	igbuio_pci_release_iomem(&udev->info);
432	if (udev->mode == RTE_INTR_MODE_MSIX)
433		pci_disable_msix(udev->pdev);
434	pci_disable_device(dev);
435fail_free:
436	kfree(udev);
437
438	return err;
439}
440
441static void
442igbuio_pci_remove(struct pci_dev *dev)
443{
444	struct rte_uio_pci_dev *udev = pci_get_drvdata(dev);
445
446	sysfs_remove_group(&dev->dev.kobj, &dev_attr_grp);
447	uio_unregister_device(&udev->info);
448	igbuio_pci_release_iomem(&udev->info);
449	if (udev->mode == RTE_INTR_MODE_MSIX)
450		pci_disable_msix(dev);
451	pci_disable_device(dev);
452	pci_set_drvdata(dev, NULL);
453	kfree(udev);
454}
455
456static int
457igbuio_config_intr_mode(char *intr_str)
458{
459	if (!intr_str) {
460		pr_info("Use MSIX interrupt by default\n");
461		return 0;
462	}
463
464	if (!strcmp(intr_str, RTE_INTR_MODE_MSIX_NAME)) {
465		igbuio_intr_mode_preferred = RTE_INTR_MODE_MSIX;
466		pr_info("Use MSIX interrupt\n");
467	} else if (!strcmp(intr_str, RTE_INTR_MODE_LEGACY_NAME)) {
468		igbuio_intr_mode_preferred = RTE_INTR_MODE_LEGACY;
469		pr_info("Use legacy interrupt\n");
470	} else {
471		pr_info("Error: bad parameter - %s\n", intr_str);
472		return -EINVAL;
473	}
474
475	return 0;
476}
477
478static struct pci_driver igbuio_pci_driver = {
479	.name = "igb_uio",
480	.id_table = NULL,
481	.probe = igbuio_pci_probe,
482	.remove = igbuio_pci_remove,
483};
484
485static int __init
486igbuio_pci_init_module(void)
487{
488	int ret;
489
490	ret = igbuio_config_intr_mode(intr_mode);
491	if (ret < 0)
492		return ret;
493
494	return pci_register_driver(&igbuio_pci_driver);
495}
496
497static void __exit
498igbuio_pci_exit_module(void)
499{
500	pci_unregister_driver(&igbuio_pci_driver);
501}
502
503module_init(igbuio_pci_init_module);
504module_exit(igbuio_pci_exit_module);
505
506module_param(intr_mode, charp, S_IRUGO);
507MODULE_PARM_DESC(intr_mode,
508"igb_uio interrupt mode (default=msix):\n"
509"    " RTE_INTR_MODE_MSIX_NAME "       Use MSIX interrupt\n"
510"    " RTE_INTR_MODE_LEGACY_NAME "     Use Legacy interrupt\n"
511"\n");
512
513MODULE_DESCRIPTION("UIO driver for Intel IGB PCI cards");
514MODULE_LICENSE("GPL");
515MODULE_AUTHOR("Intel Corporation");
516