1/*******************************************************************************
2
3  Intel(R) Gigabit Ethernet Linux driver
4  Copyright(c) 2007-2013 Intel Corporation.
5
6  This program is free software; you can redistribute it and/or modify it
7  under the terms and conditions of the GNU General Public License,
8  version 2, as published by the Free Software Foundation.
9
10  This program is distributed in the hope it will be useful, but WITHOUT
11  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13  more details.
14
15  You should have received a copy of the GNU General Public License along with
16  this program; if not, write to the Free Software Foundation, Inc.,
17  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19  The full GNU General Public License is included in this distribution in
20  the file called "LICENSE.GPL".
21
22  Contact Information:
23  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25
26*******************************************************************************/
27
28#include "e1000_api.h"
29
30/**
31 *  e1000_calculate_checksum - Calculate checksum for buffer
32 *  @buffer: pointer to EEPROM
33 *  @length: size of EEPROM to calculate a checksum for
34 *
35 *  Calculates the checksum for some buffer on a specified length.  The
36 *  checksum calculated is returned.
37 **/
38u8 e1000_calculate_checksum(u8 *buffer, u32 length)
39{
40	u32 i;
41	u8 sum = 0;
42
43	DEBUGFUNC("e1000_calculate_checksum");
44
45	if (!buffer)
46		return 0;
47
48	for (i = 0; i < length; i++)
49		sum += buffer[i];
50
51	return (u8) (0 - sum);
52}
53
54/**
55 *  e1000_mng_enable_host_if_generic - Checks host interface is enabled
56 *  @hw: pointer to the HW structure
57 *
58 *  Returns E1000_success upon success, else E1000_ERR_HOST_INTERFACE_COMMAND
59 *
60 *  This function checks whether the HOST IF is enabled for command operation
61 *  and also checks whether the previous command is completed.  It busy waits
62 *  in case of previous command is not completed.
63 **/
64s32 e1000_mng_enable_host_if_generic(struct e1000_hw *hw)
65{
66	u32 hicr;
67	u8 i;
68
69	DEBUGFUNC("e1000_mng_enable_host_if_generic");
70
71	if (!hw->mac.arc_subsystem_valid) {
72		DEBUGOUT("ARC subsystem not valid.\n");
73		return -E1000_ERR_HOST_INTERFACE_COMMAND;
74	}
75
76	/* Check that the host interface is enabled. */
77	hicr = E1000_READ_REG(hw, E1000_HICR);
78	if (!(hicr & E1000_HICR_EN)) {
79		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
80		return -E1000_ERR_HOST_INTERFACE_COMMAND;
81	}
82	/* check the previous command is completed */
83	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
84		hicr = E1000_READ_REG(hw, E1000_HICR);
85		if (!(hicr & E1000_HICR_C))
86			break;
87		msec_delay_irq(1);
88	}
89
90	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
91		DEBUGOUT("Previous command timeout failed .\n");
92		return -E1000_ERR_HOST_INTERFACE_COMMAND;
93	}
94
95	return E1000_SUCCESS;
96}
97
98/**
99 *  e1000_check_mng_mode_generic - Generic check management mode
100 *  @hw: pointer to the HW structure
101 *
102 *  Reads the firmware semaphore register and returns true (>0) if
103 *  manageability is enabled, else false (0).
104 **/
105bool e1000_check_mng_mode_generic(struct e1000_hw *hw)
106{
107	u32 fwsm = E1000_READ_REG(hw, E1000_FWSM);
108
109	DEBUGFUNC("e1000_check_mng_mode_generic");
110
111
112	return (fwsm & E1000_FWSM_MODE_MASK) ==
113		(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT);
114}
115
116/**
117 *  e1000_enable_tx_pkt_filtering_generic - Enable packet filtering on Tx
118 *  @hw: pointer to the HW structure
119 *
120 *  Enables packet filtering on transmit packets if manageability is enabled
121 *  and host interface is enabled.
122 **/
123bool e1000_enable_tx_pkt_filtering_generic(struct e1000_hw *hw)
124{
125	struct e1000_host_mng_dhcp_cookie *hdr = &hw->mng_cookie;
126	u32 *buffer = (u32 *)&hw->mng_cookie;
127	u32 offset;
128	s32 ret_val, hdr_csum, csum;
129	u8 i, len;
130
131	DEBUGFUNC("e1000_enable_tx_pkt_filtering_generic");
132
133	hw->mac.tx_pkt_filtering = true;
134
135	/* No manageability, no filtering */
136	if (!hw->mac.ops.check_mng_mode(hw)) {
137		hw->mac.tx_pkt_filtering = false;
138		return hw->mac.tx_pkt_filtering;
139	}
140
141	/* If we can't read from the host interface for whatever
142	 * reason, disable filtering.
143	 */
144	ret_val = e1000_mng_enable_host_if_generic(hw);
145	if (ret_val != E1000_SUCCESS) {
146		hw->mac.tx_pkt_filtering = false;
147		return hw->mac.tx_pkt_filtering;
148	}
149
150	/* Read in the header.  Length and offset are in dwords. */
151	len    = E1000_MNG_DHCP_COOKIE_LENGTH >> 2;
152	offset = E1000_MNG_DHCP_COOKIE_OFFSET >> 2;
153	for (i = 0; i < len; i++)
154		*(buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
155							   offset + i);
156	hdr_csum = hdr->checksum;
157	hdr->checksum = 0;
158	csum = e1000_calculate_checksum((u8 *)hdr,
159					E1000_MNG_DHCP_COOKIE_LENGTH);
160	/* If either the checksums or signature don't match, then
161	 * the cookie area isn't considered valid, in which case we
162	 * take the safe route of assuming Tx filtering is enabled.
163	 */
164	if ((hdr_csum != csum) || (hdr->signature != E1000_IAMT_SIGNATURE)) {
165		hw->mac.tx_pkt_filtering = true;
166		return hw->mac.tx_pkt_filtering;
167	}
168
169	/* Cookie area is valid, make the final check for filtering. */
170	if (!(hdr->status & E1000_MNG_DHCP_COOKIE_STATUS_PARSING))
171		hw->mac.tx_pkt_filtering = false;
172
173	return hw->mac.tx_pkt_filtering;
174}
175
176/**
177 *  e1000_mng_write_cmd_header_generic - Writes manageability command header
178 *  @hw: pointer to the HW structure
179 *  @hdr: pointer to the host interface command header
180 *
181 *  Writes the command header after does the checksum calculation.
182 **/
183s32 e1000_mng_write_cmd_header_generic(struct e1000_hw *hw,
184				      struct e1000_host_mng_command_header *hdr)
185{
186	u16 i, length = sizeof(struct e1000_host_mng_command_header);
187
188	DEBUGFUNC("e1000_mng_write_cmd_header_generic");
189
190	/* Write the whole command header structure with new checksum. */
191
192	hdr->checksum = e1000_calculate_checksum((u8 *)hdr, length);
193
194	length >>= 2;
195	/* Write the relevant command block into the ram area. */
196	for (i = 0; i < length; i++) {
197		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
198					    *((u32 *) hdr + i));
199		E1000_WRITE_FLUSH(hw);
200	}
201
202	return E1000_SUCCESS;
203}
204
205/**
206 *  e1000_mng_host_if_write_generic - Write to the manageability host interface
207 *  @hw: pointer to the HW structure
208 *  @buffer: pointer to the host interface buffer
209 *  @length: size of the buffer
210 *  @offset: location in the buffer to write to
211 *  @sum: sum of the data (not checksum)
212 *
213 *  This function writes the buffer content at the offset given on the host if.
214 *  It also does alignment considerations to do the writes in most efficient
215 *  way.  Also fills up the sum of the buffer in *buffer parameter.
216 **/
217s32 e1000_mng_host_if_write_generic(struct e1000_hw *hw, u8 *buffer,
218				    u16 length, u16 offset, u8 *sum)
219{
220	u8 *tmp;
221	u8 *bufptr = buffer;
222	u32 data = 0;
223	u16 remaining, i, j, prev_bytes;
224
225	DEBUGFUNC("e1000_mng_host_if_write_generic");
226
227	/* sum = only sum of the data and it is not checksum */
228
229	if (length == 0 || offset + length > E1000_HI_MAX_MNG_DATA_LENGTH)
230		return -E1000_ERR_PARAM;
231
232	tmp = (u8 *)&data;
233	prev_bytes = offset & 0x3;
234	offset >>= 2;
235
236	if (prev_bytes) {
237		data = E1000_READ_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset);
238		for (j = prev_bytes; j < sizeof(u32); j++) {
239			*(tmp + j) = *bufptr++;
240			*sum += *(tmp + j);
241		}
242		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset, data);
243		length -= j - prev_bytes;
244		offset++;
245	}
246
247	remaining = length & 0x3;
248	length -= remaining;
249
250	/* Calculate length in DWORDs */
251	length >>= 2;
252
253	/* The device driver writes the relevant command block into the
254	 * ram area.
255	 */
256	for (i = 0; i < length; i++) {
257		for (j = 0; j < sizeof(u32); j++) {
258			*(tmp + j) = *bufptr++;
259			*sum += *(tmp + j);
260		}
261
262		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
263					    data);
264	}
265	if (remaining) {
266		for (j = 0; j < sizeof(u32); j++) {
267			if (j < remaining)
268				*(tmp + j) = *bufptr++;
269			else
270				*(tmp + j) = 0;
271
272			*sum += *(tmp + j);
273		}
274		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, offset + i,
275					    data);
276	}
277
278	return E1000_SUCCESS;
279}
280
281/**
282 *  e1000_mng_write_dhcp_info_generic - Writes DHCP info to host interface
283 *  @hw: pointer to the HW structure
284 *  @buffer: pointer to the host interface
285 *  @length: size of the buffer
286 *
287 *  Writes the DHCP information to the host interface.
288 **/
289s32 e1000_mng_write_dhcp_info_generic(struct e1000_hw *hw, u8 *buffer,
290				      u16 length)
291{
292	struct e1000_host_mng_command_header hdr;
293	s32 ret_val;
294	u32 hicr;
295
296	DEBUGFUNC("e1000_mng_write_dhcp_info_generic");
297
298	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
299	hdr.command_length = length;
300	hdr.reserved1 = 0;
301	hdr.reserved2 = 0;
302	hdr.checksum = 0;
303
304	/* Enable the host interface */
305	ret_val = e1000_mng_enable_host_if_generic(hw);
306	if (ret_val)
307		return ret_val;
308
309	/* Populate the host interface with the contents of "buffer". */
310	ret_val = e1000_mng_host_if_write_generic(hw, buffer, length,
311						  sizeof(hdr), &(hdr.checksum));
312	if (ret_val)
313		return ret_val;
314
315	/* Write the manageability command header */
316	ret_val = e1000_mng_write_cmd_header_generic(hw, &hdr);
317	if (ret_val)
318		return ret_val;
319
320	/* Tell the ARC a new command is pending. */
321	hicr = E1000_READ_REG(hw, E1000_HICR);
322	E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
323
324	return E1000_SUCCESS;
325}
326
327/**
328 *  e1000_enable_mng_pass_thru - Check if management passthrough is needed
329 *  @hw: pointer to the HW structure
330 *
331 *  Verifies the hardware needs to leave interface enabled so that frames can
332 *  be directed to and from the management interface.
333 **/
334bool e1000_enable_mng_pass_thru(struct e1000_hw *hw)
335{
336	u32 manc;
337	u32 fwsm, factps;
338
339	DEBUGFUNC("e1000_enable_mng_pass_thru");
340
341	if (!hw->mac.asf_firmware_present)
342		return false;
343
344	manc = E1000_READ_REG(hw, E1000_MANC);
345
346	if (!(manc & E1000_MANC_RCV_TCO_EN))
347		return false;
348
349	if (hw->mac.has_fwsm) {
350		fwsm = E1000_READ_REG(hw, E1000_FWSM);
351		factps = E1000_READ_REG(hw, E1000_FACTPS);
352
353		if (!(factps & E1000_FACTPS_MNGCG) &&
354		    ((fwsm & E1000_FWSM_MODE_MASK) ==
355		     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT)))
356			return true;
357	} else if ((manc & E1000_MANC_SMBUS_EN) &&
358		   !(manc & E1000_MANC_ASF_EN)) {
359		return true;
360	}
361
362	return false;
363}
364
365/**
366 *  e1000_host_interface_command - Writes buffer to host interface
367 *  @hw: pointer to the HW structure
368 *  @buffer: contains a command to write
369 *  @length: the byte length of the buffer, must be multiple of 4 bytes
370 *
371 *  Writes a buffer to the Host Interface.  Upon success, returns E1000_SUCCESS
372 *  else returns E1000_ERR_HOST_INTERFACE_COMMAND.
373 **/
374s32 e1000_host_interface_command(struct e1000_hw *hw, u8 *buffer, u32 length)
375{
376	u32 hicr, i;
377
378	DEBUGFUNC("e1000_host_interface_command");
379
380	if (!(hw->mac.arc_subsystem_valid)) {
381		DEBUGOUT("Hardware doesn't support host interface command.\n");
382		return E1000_SUCCESS;
383	}
384
385	if (!hw->mac.asf_firmware_present) {
386		DEBUGOUT("Firmware is not present.\n");
387		return E1000_SUCCESS;
388	}
389
390	if (length == 0 || length & 0x3 ||
391	    length > E1000_HI_MAX_BLOCK_BYTE_LENGTH) {
392		DEBUGOUT("Buffer length failure.\n");
393		return -E1000_ERR_HOST_INTERFACE_COMMAND;
394	}
395
396	/* Check that the host interface is enabled. */
397	hicr = E1000_READ_REG(hw, E1000_HICR);
398	if (!(hicr & E1000_HICR_EN)) {
399		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
400		return -E1000_ERR_HOST_INTERFACE_COMMAND;
401	}
402
403	/* Calculate length in DWORDs */
404	length >>= 2;
405
406	/* The device driver writes the relevant command block
407	 * into the ram area.
408	 */
409	for (i = 0; i < length; i++)
410		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF, i,
411					    *((u32 *)buffer + i));
412
413	/* Setting this bit tells the ARC that a new command is pending. */
414	E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
415
416	for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
417		hicr = E1000_READ_REG(hw, E1000_HICR);
418		if (!(hicr & E1000_HICR_C))
419			break;
420		msec_delay(1);
421	}
422
423	/* Check command successful completion. */
424	if (i == E1000_HI_COMMAND_TIMEOUT ||
425	    (!(E1000_READ_REG(hw, E1000_HICR) & E1000_HICR_SV))) {
426		DEBUGOUT("Command has failed with no status valid.\n");
427		return -E1000_ERR_HOST_INTERFACE_COMMAND;
428	}
429
430	for (i = 0; i < length; i++)
431		*((u32 *)buffer + i) = E1000_READ_REG_ARRAY_DWORD(hw,
432								  E1000_HOST_IF,
433								  i);
434
435	return E1000_SUCCESS;
436}
437/**
438 *  e1000_load_firmware - Writes proxy FW code buffer to host interface
439 *                        and execute.
440 *  @hw: pointer to the HW structure
441 *  @buffer: contains a firmware to write
442 *  @length: the byte length of the buffer, must be multiple of 4 bytes
443 *
444 *  Upon success returns E1000_SUCCESS, returns E1000_ERR_CONFIG if not enabled
445 *  in HW else returns E1000_ERR_HOST_INTERFACE_COMMAND.
446 **/
447s32 e1000_load_firmware(struct e1000_hw *hw, u8 *buffer, u32 length)
448{
449	u32 hicr, hibba, fwsm, icr, i;
450
451	DEBUGFUNC("e1000_load_firmware");
452
453	if (hw->mac.type < e1000_i210) {
454		DEBUGOUT("Hardware doesn't support loading FW by the driver\n");
455		return -E1000_ERR_CONFIG;
456	}
457
458	/* Check that the host interface is enabled. */
459	hicr = E1000_READ_REG(hw, E1000_HICR);
460	if (!(hicr & E1000_HICR_EN)) {
461		DEBUGOUT("E1000_HOST_EN bit disabled.\n");
462		return -E1000_ERR_CONFIG;
463	}
464	if (!(hicr & E1000_HICR_MEMORY_BASE_EN)) {
465		DEBUGOUT("E1000_HICR_MEMORY_BASE_EN bit disabled.\n");
466		return -E1000_ERR_CONFIG;
467	}
468
469	if (length == 0 || length & 0x3 || length > E1000_HI_FW_MAX_LENGTH) {
470		DEBUGOUT("Buffer length failure.\n");
471		return -E1000_ERR_INVALID_ARGUMENT;
472	}
473
474	/* Clear notification from ROM-FW by reading ICR register */
475	icr = E1000_READ_REG(hw, E1000_ICR_V2);
476
477	/* Reset ROM-FW */
478	hicr = E1000_READ_REG(hw, E1000_HICR);
479	hicr |= E1000_HICR_FW_RESET_ENABLE;
480	E1000_WRITE_REG(hw, E1000_HICR, hicr);
481	hicr |= E1000_HICR_FW_RESET;
482	E1000_WRITE_REG(hw, E1000_HICR, hicr);
483	E1000_WRITE_FLUSH(hw);
484
485	/* Wait till MAC notifies about its readiness after ROM-FW reset */
486	for (i = 0; i < (E1000_HI_COMMAND_TIMEOUT * 2); i++) {
487		icr = E1000_READ_REG(hw, E1000_ICR_V2);
488		if (icr & E1000_ICR_MNG)
489			break;
490		msec_delay(1);
491	}
492
493	/* Check for timeout */
494	if (i == E1000_HI_COMMAND_TIMEOUT) {
495		DEBUGOUT("FW reset failed.\n");
496		return -E1000_ERR_HOST_INTERFACE_COMMAND;
497	}
498
499	/* Wait till MAC is ready to accept new FW code */
500	for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
501		fwsm = E1000_READ_REG(hw, E1000_FWSM);
502		if ((fwsm & E1000_FWSM_FW_VALID) &&
503		    ((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT ==
504		    E1000_FWSM_HI_EN_ONLY_MODE))
505			break;
506		msec_delay(1);
507	}
508
509	/* Check for timeout */
510	if (i == E1000_HI_COMMAND_TIMEOUT) {
511		DEBUGOUT("FW reset failed.\n");
512		return -E1000_ERR_HOST_INTERFACE_COMMAND;
513	}
514
515	/* Calculate length in DWORDs */
516	length >>= 2;
517
518	/* The device driver writes the relevant FW code block
519	 * into the ram area in DWORDs via 1kB ram addressing window.
520	 */
521	for (i = 0; i < length; i++) {
522		if (!(i % E1000_HI_FW_BLOCK_DWORD_LENGTH)) {
523			/* Point to correct 1kB ram window */
524			hibba = E1000_HI_FW_BASE_ADDRESS +
525				((E1000_HI_FW_BLOCK_DWORD_LENGTH << 2) *
526				(i / E1000_HI_FW_BLOCK_DWORD_LENGTH));
527
528			E1000_WRITE_REG(hw, E1000_HIBBA, hibba);
529		}
530
531		E1000_WRITE_REG_ARRAY_DWORD(hw, E1000_HOST_IF,
532					    i % E1000_HI_FW_BLOCK_DWORD_LENGTH,
533					    *((u32 *)buffer + i));
534	}
535
536	/* Setting this bit tells the ARC that a new FW is ready to execute. */
537	hicr = E1000_READ_REG(hw, E1000_HICR);
538	E1000_WRITE_REG(hw, E1000_HICR, hicr | E1000_HICR_C);
539
540	for (i = 0; i < E1000_HI_COMMAND_TIMEOUT; i++) {
541		hicr = E1000_READ_REG(hw, E1000_HICR);
542		if (!(hicr & E1000_HICR_C))
543			break;
544		msec_delay(1);
545	}
546
547	/* Check for successful FW start. */
548	if (i == E1000_HI_COMMAND_TIMEOUT) {
549		DEBUGOUT("New FW did not start within timeout period.\n");
550		return -E1000_ERR_HOST_INTERFACE_COMMAND;
551	}
552
553	return E1000_SUCCESS;
554}
555