1a551c94aSIdo Barnea/*******************************************************************************
2a551c94aSIdo Barnea
3a551c94aSIdo Barnea  Intel 10 Gigabit PCI Express Linux driver
4a551c94aSIdo Barnea  Copyright(c) 1999 - 2012 Intel Corporation.
5a551c94aSIdo Barnea
6a551c94aSIdo Barnea  This program is free software; you can redistribute it and/or modify it
7a551c94aSIdo Barnea  under the terms and conditions of the GNU General Public License,
8a551c94aSIdo Barnea  version 2, as published by the Free Software Foundation.
9a551c94aSIdo Barnea
10a551c94aSIdo Barnea  This program is distributed in the hope it will be useful, but WITHOUT
11a551c94aSIdo Barnea  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12a551c94aSIdo Barnea  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
13a551c94aSIdo Barnea  more details.
14a551c94aSIdo Barnea
15a551c94aSIdo Barnea  You should have received a copy of the GNU General Public License along with
16a551c94aSIdo Barnea  this program; if not, write to the Free Software Foundation, Inc.,
17a551c94aSIdo Barnea  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18a551c94aSIdo Barnea
19a551c94aSIdo Barnea  The full GNU General Public License is included in this distribution in
209ca4a157SIdo Barnea  the file called "LICENSE.GPL".
21a551c94aSIdo Barnea
22a551c94aSIdo Barnea  Contact Information:
23a551c94aSIdo Barnea  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
24a551c94aSIdo Barnea  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
25a551c94aSIdo Barnea
26a551c94aSIdo Barnea*******************************************************************************/
27a551c94aSIdo Barnea
28a551c94aSIdo Barnea#ifndef _IXGBE_FCOE_H
29a551c94aSIdo Barnea#define _IXGBE_FCOE_H
30a551c94aSIdo Barnea
31a551c94aSIdo Barnea#ifdef IXGBE_FCOE
32a551c94aSIdo Barnea
33a551c94aSIdo Barnea#include <scsi/fc/fc_fs.h>
34a551c94aSIdo Barnea#include <scsi/fc/fc_fcoe.h>
35a551c94aSIdo Barnea
36a551c94aSIdo Barnea/* shift bits within STAT fo FCSTAT */
37a551c94aSIdo Barnea#define IXGBE_RXDADV_FCSTAT_SHIFT	4
38a551c94aSIdo Barnea
39a551c94aSIdo Barnea/* ddp user buffer */
40a551c94aSIdo Barnea#define IXGBE_BUFFCNT_MAX	256	/* 8 bits bufcnt */
41a551c94aSIdo Barnea#define IXGBE_FCPTR_ALIGN	16
42a551c94aSIdo Barnea#define IXGBE_FCPTR_MAX		(IXGBE_BUFFCNT_MAX * sizeof(dma_addr_t))
43a551c94aSIdo Barnea#define IXGBE_FCBUFF_4KB	0x0
44a551c94aSIdo Barnea#define IXGBE_FCBUFF_8KB	0x1
45a551c94aSIdo Barnea#define IXGBE_FCBUFF_16KB	0x2
46a551c94aSIdo Barnea#define IXGBE_FCBUFF_64KB	0x3
47a551c94aSIdo Barnea#define IXGBE_FCBUFF_MAX	65536	/* 64KB max */
48a551c94aSIdo Barnea#define IXGBE_FCBUFF_MIN	4096	/* 4KB min */
49a551c94aSIdo Barnea#define IXGBE_FCOE_DDP_MAX	512	/* 9 bits xid */
50a551c94aSIdo Barnea
51a551c94aSIdo Barnea/* Default traffic class to use for FCoE */
52a551c94aSIdo Barnea#define IXGBE_FCOE_DEFTC	3
53a551c94aSIdo Barnea
54a551c94aSIdo Barnea/* fcerr */
55a551c94aSIdo Barnea#define IXGBE_FCERR_BADCRC	0x00100000
56a551c94aSIdo Barnea#define IXGBE_FCERR_EOFSOF	0x00200000
57a551c94aSIdo Barnea#define IXGBE_FCERR_NOFIRST	0x00300000
58a551c94aSIdo Barnea#define IXGBE_FCERR_OOOSEQ	0x00400000
59a551c94aSIdo Barnea#define IXGBE_FCERR_NODMA	0x00500000
60a551c94aSIdo Barnea#define IXGBE_FCERR_PKTLOST	0x00600000
61a551c94aSIdo Barnea
62a551c94aSIdo Barnea/* FCoE DDP for target mode */
63a551c94aSIdo Barnea#define __IXGBE_FCOE_TARGET	1
64a551c94aSIdo Barnea
65a551c94aSIdo Barneastruct ixgbe_fcoe_ddp {
66a551c94aSIdo Barnea	int len;
67a551c94aSIdo Barnea	u32 err;
68a551c94aSIdo Barnea	unsigned int sgc;
69a551c94aSIdo Barnea	struct scatterlist *sgl;
70a551c94aSIdo Barnea	dma_addr_t udp;
71a551c94aSIdo Barnea	u64 *udl;
72a551c94aSIdo Barnea	struct pci_pool *pool;
73a551c94aSIdo Barnea};
74a551c94aSIdo Barnea
75a551c94aSIdo Barneastruct ixgbe_fcoe {
76a551c94aSIdo Barnea	struct pci_pool **pool;
77a551c94aSIdo Barnea	atomic_t refcnt;
78a551c94aSIdo Barnea	spinlock_t lock;
79a551c94aSIdo Barnea	struct ixgbe_fcoe_ddp ddp[IXGBE_FCOE_DDP_MAX];
80a551c94aSIdo Barnea	unsigned char *extra_ddp_buffer;
81a551c94aSIdo Barnea	dma_addr_t extra_ddp_buffer_dma;
82a551c94aSIdo Barnea	u64 __percpu *pcpu_noddp;
83a551c94aSIdo Barnea	u64 __percpu *pcpu_noddp_ext_buff;
84a551c94aSIdo Barnea	unsigned long mode;
85a551c94aSIdo Barnea	u8 tc;
86a551c94aSIdo Barnea	u8 up;
87a551c94aSIdo Barnea	u8 up_set;
88a551c94aSIdo Barnea};
89a551c94aSIdo Barnea#endif /* IXGBE_FCOE */
90a551c94aSIdo Barnea
91a551c94aSIdo Barnea#endif /* _IXGBE_FCOE_H */
92