1/*
2  Copyright (c) 2016-2016 Cisco Systems, Inc.
3
4  Licensed under the Apache License, Version 2.0 (the "License");
5  you may not use this file except in compliance with the License.
6  You may obtain a copy of the License at
7
8  http://www.apache.org/licenses/LICENSE-2.0
9
10  Unless required by applicable law or agreed to in writing, software
11  distributed under the License is distributed on an "AS IS" BASIS,
12  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13  See the License for the specific language governing permissions and
14  limitations under the License.
15*/
16
17#include <stdint.h>
18#include <rte_byteorder.h>
19#include <rte_ethdev.h>
20#include "dpdk/drivers/net/i40e/base/i40e_register.h"
21#include "dpdk/drivers/net/i40e/base/i40e_status.h"
22#include "dpdk/drivers/net/i40e/base/i40e_osdep.h"
23#include "dpdk/drivers/net/i40e/base/i40e_type.h"
24#include "dpdk/drivers/net/i40e/i40e_ethdev.h"
25#include "dpdk_funcs.h"
26
27void i40e_trex_dump_fdir_regs(struct i40e_hw *hw)
28{
29    int reg_nums[] = {31, 33, 34, 35, 41, 43};
30    int i;
31    uint32_t reg;
32
33    for (i =0; i < sizeof (reg_nums)/sizeof(int); i++) {
34	reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(reg_nums[i], 0));
35        printf("I40E_PRTQF_FD_INSET(%d, 0): 0x%08x\n", reg_nums[i], reg);
36	reg = I40E_READ_REG(hw,I40E_PRTQF_FD_INSET(reg_nums[i], 1));
37        printf("I40E_PRTQF_FD_INSET(%d, 1): 0x%08x\n", reg_nums[i], reg);
38    }
39}
40
41void i40e_trex_fdir_reg_init(int port_id, int mode)
42{
43    struct rte_eth_dev *dev = &rte_eth_devices[port_id];
44	struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
45
46	I40E_WRITE_REG(hw, I40E_GLQF_ORT(12), 0x00000062);
47	I40E_WRITE_REG(hw, I40E_GLQF_PIT(2), 0x000024A0);
48	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_UDP, 0), 0);
49	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_TCP, 0), 0);
50	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, 0), 0);
51	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_UDP, 0), 0);
52	I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_TCP, 0), 0);
53    I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER, 0), 0);
54    switch(mode) {
55    case I40E_TREX_INIT_STL:
56        // stateless - filter according to IP id or IPv6 identification
57        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_UDP, 1), 0x00100000);
58        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_TCP, 1), 0x00100000);
59        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, 1), 0x00100000);
60        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_UDP, 1),   0x0000000000200000ULL);
61        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_TCP, 1),   0x0000000000200000ULL);
62        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER, 1), 0x0000000000200000ULL);
63        break;
64    case I40E_TREX_INIT_RCV_ALL:
65        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_UDP, 1), 0);
66        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_TCP, 1), 0);
67        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, 1), 0);
68        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_UDP, 1), 0);
69        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_TCP, 1), 0);
70        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER, 1), 0);
71        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, 0), 0);
72        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, 1), 0);
73        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP, 0), 0);
74        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP, 1), 0);
75        break;
76    case I40E_TREX_INIT_STF:
77    default:
78        // stateful - Filter according to TTL or IPv6 hop limit
79        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_UDP, 1), 0x00040000);
80        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_TCP, 1), 0x00040000);
81        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER, 1), 0x00040000);
82        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_UDP, 1), 0x00080000);
83        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_TCP, 1), 0x00080000);
84        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER, 1), 0x00080000);
85        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, 0), 0);
86        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP, 1), 0x00040000);
87        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP, 0), 0);
88        I40E_WRITE_REG(hw, I40E_PRTQF_FD_INSET(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP, 1), 0x00080000);
89        break;
90    }
91	I40E_WRITE_REG(hw, I40E_GLQF_FD_MSK(0, 34), 0x000DFF00);
92	I40E_WRITE_REG(hw, I40E_GLQF_FD_MSK(0,44), 0x000C00FF);
93	I40E_WRITE_FLUSH(hw);
94}
95
96// fill stats array with fdir rules match count statistics
97// Notice that we read statistics from start to start + len, but we fill the stats are
98//  starting from 0 with len values
99void
100i40e_trex_fdir_stats_get(struct rte_eth_dev *dev, uint32_t *stats, uint32_t start, uint32_t len)
101{
102    int i;
103    struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
104
105    for (i = 0; i < len; i++) {
106        stats[i] = I40E_READ_REG(hw, I40E_GLQF_PCNT(i + start));
107    }
108}
109
110void
111i40e_trex_fdir_stats_reset(struct rte_eth_dev *dev, uint32_t *stats, uint32_t start, uint32_t len)
112{
113    int i;
114    struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
115
116    for (i = 0; i < len; i++) {
117        if (stats) {
118            stats[i] = I40E_READ_REG(hw, I40E_GLQF_PCNT(i + start));
119        }
120        I40E_WRITE_REG(hw, I40E_GLQF_PCNT(i + start), 0xffffffff);
121    }
122}
123
124int
125i40e_trex_get_fw_ver(struct rte_eth_dev *dev, uint32_t *nvm_ver)
126{
127    struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
128
129    *nvm_ver = hw->nvm.version;
130    return 0;
131}
132
133/* This function existed in older DPDK versions. We keep it */
134int
135rte_eth_dev_get_port_by_addr(const struct rte_pci_addr *addr, uint8_t *port_id)
136{
137	int i;
138	struct rte_pci_device *pci_dev = NULL;
139
140	if (addr == NULL) {
141		RTE_PMD_DEBUG_TRACE("Null pointer is specified\n");
142		return -EINVAL;
143	}
144
145	*port_id = RTE_MAX_ETHPORTS;
146
147	for (i = 0; i < RTE_MAX_ETHPORTS; i++) {
148		if (
149			!rte_eal_compare_pci_addr(&rte_eth_devices[i].device->devargs->pci.addr, addr)) {
150
151			*port_id = i;
152
153			return 0;
154		}
155	}
156	return -ENODEV;
157}
158
159// return in stats, statistics starting from start, for len counters.
160int
161rte_eth_fdir_stats_get(uint8_t port_id, uint32_t *stats, uint32_t start, uint32_t len)
162{
163	struct rte_eth_dev *dev;
164
165	RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
166
167	dev = &rte_eth_devices[port_id];
168
169    // Only xl710 support this
170    i40e_trex_fdir_stats_get(dev, stats, start, len);
171
172    return 0;
173}
174
175// zero statistics counters, starting from start, for len counters.
176int
177rte_eth_fdir_stats_reset(uint8_t port_id, uint32_t *stats, uint32_t start, uint32_t len)
178{
179	struct rte_eth_dev *dev;
180
181	RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
182
183	dev = &rte_eth_devices[port_id];
184
185    // Only xl710 support this
186    i40e_trex_fdir_stats_reset(dev, stats, start, len);
187
188    return 0;
189}
190
191int
192rte_eth_get_fw_ver(int port_id, uint32_t *version)
193{
194	struct rte_eth_dev *dev;
195
196	RTE_ETH_VALID_PORTID_OR_ERR_RET(port_id, -EINVAL);
197
198	dev = &rte_eth_devices[port_id];
199
200    // Only xl710 support this
201    return i40e_trex_get_fw_ver(dev, version);
202}
203