trex_stateless_rx_core.h revision d0c838e0
1/*
2  Ido Barnea
3  Cisco Systems, Inc.
4*/
5
6/*
7  Copyright (c) 2016-2016 Cisco Systems, Inc.
8
9  Licensed under the Apache License, Version 2.0 (the "License");
10  you may not use this file except in compliance with the License.
11  You may obtain a copy of the License at
12
13  http://www.apache.org/licenses/LICENSE-2.0
14
15  Unless required by applicable law or agreed to in writing, software
16  distributed under the License is distributed on an "AS IS" BASIS,
17  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
18  See the License for the specific language governing permissions and
19  limitations under the License.
20*/
21#ifndef __TREX_STATELESS_RX_CORE_H__
22#define __TREX_STATELESS_RX_CORE_H__
23#include <stdint.h>
24#include "stateful_rx_core.h"
25#include "os_time.h"
26#include "pal/linux/sanb_atomic.h"
27#include "utl_cpuu.h"
28#include "trex_stateless_rx_port_mngr.h"
29
30class TrexStatelessCpToRxMsgBase;
31
32
33class CRFC2544Info {
34 public:
35    void create();
36    void stop();
37    void reset();
38    void export_data(rfc2544_info_t_ &obj);
39    inline void add_sample(double stime) {
40        m_latency.Add(stime);
41        m_jitter.calc(stime);
42    }
43    inline void sample_period_end() {
44        m_latency.update();
45    }
46    inline uint32_t get_seq() {return m_seq;}
47    inline void set_seq(uint32_t val) {m_seq = val;}
48    inline void inc_seq_err(uint64_t val) {m_seq_err += val;}
49    inline void dec_seq_err() {if (m_seq_err >0) {m_seq_err--;}}
50    inline void inc_seq_err_too_big() {m_seq_err_events_too_big++;}
51    inline void inc_seq_err_too_low() {m_seq_err_events_too_low++;}
52    inline void inc_dup() {m_dup++;}
53    inline void inc_ooo() {m_ooo++;}
54    inline uint16_t get_exp_flow_seq() {return m_exp_flow_seq;}
55    inline void set_exp_flow_seq(uint16_t flow_seq) {m_exp_flow_seq = flow_seq;}
56    inline uint16_t get_prev_flow_seq() {return m_prev_flow_seq;}
57    inline bool no_flow_seq() {return (m_exp_flow_seq == FLOW_STAT_PAYLOAD_INITIAL_FLOW_SEQ) ? true : false;}
58 private:
59    uint32_t m_seq; // expected next seq num
60    CTimeHistogram  m_latency; // latency info
61    CJitter         m_jitter;
62    uint64_t m_seq_err; // How many packet seq num gaps we saw (packets lost or out of order)
63    uint64_t m_seq_err_events_too_big; // How many packet seq num greater than expected events we had
64    uint64_t m_seq_err_events_too_low; // How many packet seq num lower than expected events we had
65    uint64_t m_ooo; // Packets we got with seq num lower than expected (We guess they are out of order)
66    uint64_t m_dup; // Packets we got with same seq num
67    uint16_t m_exp_flow_seq; // flow sequence number we should see in latency header
68    // flow sequence number previously used with this id. We use this to catch packets arriving late from an old flow
69    uint16_t m_prev_flow_seq;
70};
71
72class CRxCoreErrCntrs {
73    friend CRxCoreStateless;
74
75 public:
76    uint64_t get_bad_header() {return m_bad_header;}
77    uint64_t get_old_flow() {return m_old_flow;}
78    CRxCoreErrCntrs() {
79        reset();
80    }
81    void reset() {
82        m_bad_header = 0;
83        m_old_flow = 0;
84    }
85
86 public:
87    uint64_t m_bad_header;
88    uint64_t m_old_flow;
89};
90
91class CRxCoreStateless {
92    enum state_e {
93        STATE_IDLE,
94        STATE_WORKING,
95        STATE_QUIT
96    };
97
98 public:
99    void start();
100    void create(const CRxSlCfg &cfg);
101    void reset_rx_stats(uint8_t port_id);
102    int get_rx_stats(uint8_t port_id, rx_per_flow_t *rx_stats, int min, int max, bool reset
103                     , TrexPlatformApi::driver_stat_cap_e type);
104    int get_rfc2544_info(rfc2544_info_t *rfc2544_info, int min, int max, bool reset);
105    int get_rx_err_cntrs(CRxCoreErrCntrs *rx_err);
106
107
108    void quit() {m_state = STATE_QUIT;}
109    bool is_working() const {return (m_ack_start_work_msg == true);}
110    void set_working_msg_ack(bool val);
111    double get_cpu_util();
112    void update_cpu_util();
113
114    RXPacketBuffer *get_rx_queue_pkts(uint8_t port_id) {
115        return m_rx_port_mngr[port_id].get_pkt_buffer();
116    }
117
118    /**
119     * start capturing of RX packets on a specific port
120     *
121     * @author imarom (11/2/2016)
122     *
123     * @param port_id
124     * @param pcap_filename
125     * @param limit
126     */
127    void start_capture(uint8_t port_id, const std::string &pcap_filename, uint64_t limit, uint64_t *shared_counter);
128    void stop_capture(uint8_t port_id);
129
130    /**
131     * start RX queueing of packets
132     *
133     */
134    void start_queue(uint8_t port_id, uint64_t size, uint64_t *shared_counter);
135    void stop_queue(uint8_t port_id);
136
137    /**
138     * enable latency feature for RX packets
139     * will be apply to all ports
140     */
141    void enable_latency();
142    void disable_latency();
143
144 private:
145    void handle_cp_msg(TrexStatelessCpToRxMsgBase *msg);
146    bool periodic_check_for_cp_messages();
147    void tickle();
148    void idle_state_loop();
149
150    void recalculate_next_state();
151    bool are_any_features_active();
152
153    void capture_pkt(rte_mbuf_t *m);
154    void handle_rx_queue_msgs(uint8_t thread_id, CNodeRing * r);
155    void handle_work_stage(bool do_try_rx_queue);
156
157    int process_all_pending_pkts(bool flush_rx = false);
158
159    void flush_all_pending_pkts() {
160        process_all_pending_pkts(true);
161    }
162
163    void try_rx_queues();
164
165 private:
166    TrexMonitor      m_monitor;
167    uint32_t         m_max_ports;
168    bool             m_capture;
169    state_e          m_state;
170    CNodeRing       *m_ring_from_cp;
171    CNodeRing       *m_ring_to_cp;
172    CCpuUtlDp        m_cpu_dp_u;
173    CCpuUtlCp        m_cpu_cp_u;
174
175    // Used for acking "work" (go out of idle) messages from cp
176    volatile bool m_ack_start_work_msg __rte_cache_aligned;
177
178    CRxCoreErrCntrs m_err_cntrs;
179    CRFC2544Info m_rfc2544[MAX_FLOW_STATS_PAYLOAD];
180
181    RXPortManager m_rx_port_mngr[TREX_MAX_PORTS];
182};
183#endif
184