1dd648aacSDamjan Marion/*
2dd648aacSDamjan Marion *------------------------------------------------------------------
3dd648aacSDamjan Marion * Copyright (c) 2020 Cisco and/or its affiliates.
4dd648aacSDamjan Marion * Licensed under the Apache License, Version 2.0 (the "License");
5dd648aacSDamjan Marion * you may not use this file except in compliance with the License.
6dd648aacSDamjan Marion * You may obtain a copy of the License at:
7dd648aacSDamjan Marion *
8dd648aacSDamjan Marion *     http://www.apache.org/licenses/LICENSE-2.0
9dd648aacSDamjan Marion *
10dd648aacSDamjan Marion * Unless required by applicable law or agreed to in writing, software
11dd648aacSDamjan Marion * distributed under the License is distributed on an "AS IS" BASIS,
12dd648aacSDamjan Marion * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13dd648aacSDamjan Marion * See the License for the specific language governing permissions and
14dd648aacSDamjan Marion * limitations under the License.
15dd648aacSDamjan Marion *------------------------------------------------------------------
16dd648aacSDamjan Marion */
17dd648aacSDamjan Marion
18dd648aacSDamjan Marion#ifndef _RDMA_MLX5DV_H_
19dd648aacSDamjan Marion#define _RDMA_MLX5DV_H_
20dd648aacSDamjan Marion
21dd648aacSDamjan Marion#undef always_inline
22dd648aacSDamjan Marion#include <infiniband/mlx5dv.h>
23dd648aacSDamjan Marion#define always_inline static_always_inline
24dd648aacSDamjan Marion
25dd648aacSDamjan Marion/* CQE flags - bits 16-31 of qword at offset 0x1c */
26dd648aacSDamjan Marion#define CQE_FLAG_L4_OK			10
27dd648aacSDamjan Marion#define CQE_FLAG_L3_OK			9
28dd648aacSDamjan Marion#define CQE_FLAG_L2_OK			8
29dd648aacSDamjan Marion#define CQE_FLAG_IP_FRAG		7
30dd648aacSDamjan Marion#define CQE_FLAG_L4_HDR_TYPE(f)		(((f) >> 4) & 7)
31dd648aacSDamjan Marion#define CQE_FLAG_L3_HDR_TYPE_SHIFT	(2)
32dd648aacSDamjan Marion#define CQE_FLAG_L3_HDR_TYPE_MASK	(3 << CQE_FLAG_L3_HDR_TYPE_SHIFT)
33dd648aacSDamjan Marion#define CQE_FLAG_L3_HDR_TYPE(f)		(((f) & CQE_FLAG_L3_HDR_TYPE_MASK)  >> CQE_FLAG_L3_HDR_TYPE_SHIFT)
34dd648aacSDamjan Marion#define CQE_FLAG_L3_HDR_TYPE_IP4	1
35dd648aacSDamjan Marion#define CQE_FLAG_L3_HDR_TYPE_IP6	2
36dd648aacSDamjan Marion#define CQE_FLAG_IP_EXT_OPTS		1
37dd648aacSDamjan Marion
38dd648aacSDamjan Mariontypedef struct
39dd648aacSDamjan Marion{
40dd648aacSDamjan Marion  struct
41dd648aacSDamjan Marion  {
42dd648aacSDamjan Marion    u8 pad1[28];
43dd648aacSDamjan Marion    u16 flags;
44dd648aacSDamjan Marion    u8 pad2[14];
45dd648aacSDamjan Marion    union
46dd648aacSDamjan Marion    {
47dd648aacSDamjan Marion      u32 byte_cnt;
48dd648aacSDamjan Marion      u32 mini_cqe_num;
49dd648aacSDamjan Marion    };
50dd648aacSDamjan Marion    u8 pad3[15];
51dd648aacSDamjan Marion    u8 opcode_cqefmt_se_owner;
52dd648aacSDamjan Marion  };
53dd648aacSDamjan Marion} mlx5dv_cqe_t;
54dd648aacSDamjan Marion
55dd648aacSDamjan MarionSTATIC_ASSERT_SIZEOF (mlx5dv_cqe_t, 64);
56dd648aacSDamjan Marion
57dd648aacSDamjan Mariontypedef struct
58dd648aacSDamjan Marion{
59dd648aacSDamjan Marion  union
60dd648aacSDamjan Marion  {
61dd648aacSDamjan Marion    u32 checksum;
62dd648aacSDamjan Marion    u32 rx_hash_result;
63dd648aacSDamjan Marion  };
64dd648aacSDamjan Marion  u32 byte_count;
65dd648aacSDamjan Marion} mlx5dv_mini_cqe_t;
66dd648aacSDamjan Marion
67dd648aacSDamjan Mariontypedef struct
68dd648aacSDamjan Marion{
69dd648aacSDamjan Marion  u64 dsz_and_lkey;
70dd648aacSDamjan Marion  u64 addr;
71dd648aacSDamjan Marion} mlx5dv_rwq_t;
72dd648aacSDamjan Marion
73dd648aacSDamjan Marion#define foreach_cqe_rx_field \
74dd648aacSDamjan Marion  _(0x1c, 26, 26, l4_ok)	\
75dd648aacSDamjan Marion  _(0x1c, 25, 25, l3_ok)	\
76dd648aacSDamjan Marion  _(0x1c, 24, 24, l2_ok)	\
77dd648aacSDamjan Marion  _(0x1c, 23, 23, ip_frag)	\
78dd648aacSDamjan Marion  _(0x1c, 22, 20, l4_hdr_type)	\
79dd648aacSDamjan Marion  _(0x1c, 19, 18, l3_hdr_type)	\
80dd648aacSDamjan Marion  _(0x1c, 17, 17, ip_ext_opts)	\
81dd648aacSDamjan Marion  _(0x1c, 16, 16, cv)	\
82dd648aacSDamjan Marion  _(0x2c, 31,  0, byte_cnt)	\
83dd648aacSDamjan Marion  _(0x30, 63,  0, timestamp)	\
84dd648aacSDamjan Marion  _(0x38, 31, 24, rx_drop_counter)	\
85dd648aacSDamjan Marion  _(0x38, 23,  0, flow_tag)	\
86dd648aacSDamjan Marion  _(0x3c, 31, 16, wqe_counter)	\
87dd648aacSDamjan Marion  _(0x3c, 15,  8, signature)	\
88dd648aacSDamjan Marion  _(0x3c,  7,  4, opcode)	\
89dd648aacSDamjan Marion  _(0x3c,  3,  2, cqe_format)	\
90dd648aacSDamjan Marion  _(0x3c,  1,  1, sc)	\
91dd648aacSDamjan Marion  _(0x3c,  0,  0, owner)
92dd648aacSDamjan Marion
93dd648aacSDamjan Marion
94dd648aacSDamjan Marion/* inline functions */
95dd648aacSDamjan Marion
96dd648aacSDamjan Marionstatic inline u32
97dd648aacSDamjan Marionmlx5_get_u32 (void *start, int offset)
98dd648aacSDamjan Marion{
99dd648aacSDamjan Marion  return clib_net_to_host_u32 (*(u32 *) (((u8 *) start) + offset));
100dd648aacSDamjan Marion}
101dd648aacSDamjan Marion
102dd648aacSDamjan Marionstatic inline u64
103dd648aacSDamjan Marionmlx5_get_u64 (void *start, int offset)
104dd648aacSDamjan Marion{
105dd648aacSDamjan Marion  return clib_net_to_host_u64 (*(u64 *) (((u8 *) start) + offset));
106dd648aacSDamjan Marion}
107dd648aacSDamjan Marion
108dd648aacSDamjan Marionstatic inline void
109dd648aacSDamjan Marionmlx5_set_u32 (void *start, int offset, u32 value)
110dd648aacSDamjan Marion{
111dd648aacSDamjan Marion  (*(u32 *) (((u8 *) start) + offset)) = clib_host_to_net_u32 (value);
112dd648aacSDamjan Marion}
113dd648aacSDamjan Marion
114dd648aacSDamjan Marionstatic inline void
115dd648aacSDamjan Marionmlx5_set_u64 (void *start, int offset, u64 value)
116dd648aacSDamjan Marion{
117dd648aacSDamjan Marion  (*(u64 *) (((u8 *) start) + offset)) = clib_host_to_net_u64 (value);
118dd648aacSDamjan Marion}
119dd648aacSDamjan Marion
120dd648aacSDamjan Marionstatic inline void
121dd648aacSDamjan Marionmlx5_set_bits (void *start, int offset, int first, int last, u32 value)
122dd648aacSDamjan Marion{
123dd648aacSDamjan Marion  u32 mask = (1 << (first - last + 1)) - 1;
124dd648aacSDamjan Marion  u32 old = mlx5_get_u32 (start, offset);
125dd648aacSDamjan Marion  if ((last == 0) && (first == 31))
126dd648aacSDamjan Marion    {
127dd648aacSDamjan Marion      mlx5_set_u32 (start, offset, value);
128dd648aacSDamjan Marion      return;
129dd648aacSDamjan Marion    }
130dd648aacSDamjan Marion  ASSERT (value == (value & mask));
131dd648aacSDamjan Marion  value &= mask;
132dd648aacSDamjan Marion  old &= ~(mask << last);
133dd648aacSDamjan Marion  mlx5_set_u32 (start, offset, old | value << last);
134dd648aacSDamjan Marion}
135dd648aacSDamjan Marion
136dd648aacSDamjan Marionstatic inline u32
137dd648aacSDamjan Marionmlx5_get_bits (void *start, int offset, int first, int last)
138dd648aacSDamjan Marion{
139dd648aacSDamjan Marion  u32 value = mlx5_get_u32 (start, offset);
140dd648aacSDamjan Marion  if ((last == 0) && (first == 31))
141dd648aacSDamjan Marion    return value;
142dd648aacSDamjan Marion  value >>= last;
143dd648aacSDamjan Marion  value &= (1 << (first - last + 1)) - 1;
144dd648aacSDamjan Marion  return value;
145dd648aacSDamjan Marion}
146dd648aacSDamjan Marion
147dd648aacSDamjan Marion
148dd648aacSDamjan Marion#endif /* RDMA_MLX5DV_H */
149dd648aacSDamjan Marion
150dd648aacSDamjan Marion/*
151dd648aacSDamjan Marion * fd.io coding-style-patch-verification: ON
152dd648aacSDamjan Marion *
153dd648aacSDamjan Marion * Local Variables:
154dd648aacSDamjan Marion * eval: (c-set-style "gnu")
155dd648aacSDamjan Marion * End:
156dd648aacSDamjan Marion */
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